Method for implementing content-addressable memory based on ambipolar FET

Patent metadata

Field	Value
Publication number	US-12567464-B2
Application number	US-202318715959-A
Country	US
Kind code	B2
Filing date	Apr 24, 2023
Priority date	Sep 22, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Disclosed is a method for implementing a content addressable memory based on an ambipolar FET, wherein a linear non-separable comparison operation required for a CAM cell is realized based on a single ambipolar FET with a threshold voltage through interposing a memory layer between a gate dielectric layer and a control gate of the ambipolar FET in source/drain symmetry to modulate the threshold voltage for information storage and through utilizing its non-monotonic transfer characteristics for input search.

First claim

What is claimed is:

1 . A method for implementing a CAM based on an ambipolar FET, characterized by
1) using a semiconductor material with ambipolar conductive characteristics of electrons and holes as a channel, or a metal or metal silicide as a source/drain material, so that the FET with a source/drain-symmetric structure exhibits a non-monotonic ambipolar transfer characteristics; 2) interposing a memory layer between a gate dielectric layer and a control gate of the ambipolar FET, wherein the memory layer uses a floating gate/charge trapping layer and a tunneling dielectric layer to modulate a threshold voltage of the transistor through trapping/de-trapping charges in the semiconductor channel, or uses a layer of a ferroelectric material to modulate the threshold voltage of the transistor by switching a polarization state of the ferroelectric material, so that the ambipolar FET with a modulatable threshold voltage, represented as AMFET, is formed; and 3) forming the CAM cell with the AMFET obtained in step 2); 4) wherein a drain and a gate of the AMFET are used as a ML terminal and a SL terminal of the CAM, respectively, and a source of the AMFET is grounded, wherein in a stage of performing write on the CAM cell to store an entry, the ML terminal is grounded, and programming or erasing voltage pulses are applied to the SL terminal to modulate the threshold voltage of the AMFET by charge trapping/charge de-trapping or ferroelectric polarization switching, so that a translation along a gate voltage is exhibited on a transfer characteristic curve of the device, where the gate voltage corresponding to a minimum drain current is called V OFF , and corresponding V OFF0 and V OFF1 after a programming/erasing operation represent storing of entry 0 and entry 1, respectively; and in a searching operation, DC voltage biases of V SL0 and V SL1 are applied, representing inputting of query 0 and query 1, respectively, to the SL terminal and a fixed read voltage is applied to the ML terminal to determine a matching result by detecting a current of the ML terminal, wherein only when the input query is identical to the stored entries, the AMFET is in a turn-off state with a lower drain current, indicating match, and when the input query is not identical to the stored entries, the AMFET is in a turn-on state with a higher drain current, indicating mismatch, then the searching operation and the matching operation of a CAM cell is completed.

2 . The method for implementing the CAM based on the ambipolar FET according to claim 1 , characterized in that the semiconductor material in step 1) is an organic small molecule, a polymer, a two-dimensional material, an oxide, and an organic-inorganic hybrid material.

3 . The method for implementing CAM based on the ambipolar FET according to claim 1 , characterized in that the ferroelectric material in step 2) is HfO 2 doped with Zr (HZO), HfO 2 doped with Al (HfAlO), or a chalcocite-type ferroelectric or a ferroelectric polymer.

4 . The method for implementing CAM based on the ambipolar FET according to claim 1 , characterized in that a gate stack on the gate dielectric layer is based on an MFMIS, MFIS, MFS structure.

5 . The method for implementing CAM based on the ambipolar FET according to claim 1 , characterized in that the CAM cells form an array, and each row of CAM cells in the array shares a ML, wherein a corresponding search voltage is applied to all of the SL terminals at the same time according to an input vector of the query, and each of rows of MLs for the CAM array has a different magnitude of current according to various mismatch situations between the input vector of query and stored vectors of entries, the magnitude of which is proportional to a degree of the mismatch, and a distance metric is realized according to the magnitude of this current.

Assignees

• Univ Beijing

Inventors

• Huang Ru
• Xu Weikai
• Luo Jin
• Huang Qianqian

Classifications

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/225

  Auxiliary circuits · CPC title

• G11C15/046 Primary

  using non-volatile storage elements · CPC title

• G11C11/223 Primary

  using MOS with ferroelectric gate insulating film · CPC title