Ternary neural network accelerator device and method of operating the same

Patent metadata

Field	Value
Publication number	US-12566949-B2
Application number	US-202318303941-A
Country	US
Kind code	B2
Filing date	Apr 20, 2023
Priority date	Jul 28, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

According to one aspect of the present invention, a ternary neural network accelerator device includes a first semiconductor device comprising a first source terminal, a first drain terminal, and a first gate terminal, a second semiconductor device comprising a second source terminal, a second drain terminal, and a second gate terminal, a first searching line connected to the first drain terminal, a second searching line connected to the second drain terminal, and a matching line commonly connected to the first source terminal and the second source terminal, wherein ternary weight and ternary input are each set by either of a first operation and a second operation and nine computation results are output through the matching line according to conditions of the ternary weight and ternary input.

First claim

What is claimed is:

1 . A ternary neural network accelerator device, comprising:
a first semiconductor device comprising a first source terminal, a first drain terminal, and a first gate terminal; a second semiconductor device comprising a second source terminal, a second drain terminal, and a second gate terminal; a first searching line connected to the first drain terminal; a second searching line connected to the second drain terminal; and a matching line commonly connected to the first source terminal and the second source terminal, wherein ternary weight and ternary input are each set by either of a first operation in which a first threshold voltage of the first semiconductor device and a second threshold voltage of the second semiconductor device is changed to one of three states obtained by combining a relatively low threshold voltage and a relatively high threshold voltage and a second operation in which voltages to be applied to the first searching line and the second searching line are set to one of three combinations of a ground voltage, an operating voltage, and an intermediate operating voltage, and nine computation results are output through the matching line according to conditions of the ternary weight and the ternary input.

2 . The ternary neural network accelerator device of claim 1 , wherein in the first operation, the three states comprises a first state in which both the first threshold voltage and the second threshold voltage are high threshold voltages; a second state in which the first threshold voltage is a high threshold voltage and the second threshold voltage is a low threshold voltage; and a third state in which the first threshold voltage is a low threshold voltage and the second threshold voltage is a high threshold voltage.

3 . The ternary neural network accelerator device of claim 1 , wherein in the second operation, the three combinations comprises a first combination by which the intermediate operating voltage is applied to both the first searching line and the second searching line; a second combination by which the ground voltage is applied to the first searching line and the operating voltage is applied to the second searching line; and a third combination by which the operating voltage is applied to the first searching line and the ground voltage is applied to the second searching line.

4 . The ternary neural network accelerator device of claim 1 , wherein the ternary weight is set by the first operation and the ternary input is set by the second operation.

5 . The ternary neural network accelerator device of claim 1 , wherein the ternary weight is set by the second operation and the ternary input is set by the first operation.

6 . The ternary neural network accelerator device of claim 1 , wherein the matching line is precharged to the intermediate operating voltage.

7 . The ternary neural network accelerator device of claim 1 , wherein the first semiconductor device and the second semiconductor device are ferroelectric field effect transistors (FeFET).

8 . The ternary neural network accelerator device of claim 7 , wherein in the first operation, the high threshold voltage is a threshold voltage in a programmed state of the FeFET and the low threshold voltage is a threshold voltage in an erase state of the FeFET.

9 . The ternary neural network accelerator device of claim 1 , wherein the first semiconductor device and the second semiconductor device are flash memory devices.

10 . A method of operating a ternary neural network accelerator device which comprises a first semiconductor device comprising a first source terminal, a first drain terminal, and a first gate terminal; a second semiconductor device comprising a second source terminal, a second drain terminal, and a second gate terminal; a first searching line connected to the first drain terminal; a second searching line connected to the second drain terminal; and a matching line commonly connected to the first source terminal and the second source terminal, the method comprising:
setting conditions of ternary weight and ternary input in the ternary neural network accelerator device; and performing a ternary operation of outputting nine computation results through the matching line according to the conditions of the ternary weight and ternary input, wherein the ternary weight and the ternary input are each set by either of a first operation in which a first threshold voltage of the first semiconductor device and a second threshold voltage of the second semiconductor device is changed to one of three states obtained by combining a relatively low threshold voltage and a relatively high threshold voltage and a second operation in which voltages to be applied to the first searching line and the second searching line are set to one of three combinations of a ground voltage, an operating voltage, and an intermediate operating voltage.

Assignees

• Univ Inha Res & Business Found

Inventors

• Seo Yeongkyo
• Kwon Dae Woong

Classifications

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title