Ternary computation memory systems and circuits employing binary bit cell-XNOR circuits particularly suited to deep neural network (DNN) computing

Patent metadata

Field	Value
Publication number	US-11126402-B2
Application number	US-201916360698-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 21, 2019
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A multiply-accumulate (MAC) operation in a deep neural network (DNN) consists of multiplying each input signal to a node by a respective numerical weight data and summing the products. Using ternary values for the input signals and weight data reduces memory and processing resources significantly. By representing ternary values in two-bit binary form, MAC operations can be replaced with logic operations (e.g., XNOR, popcount) implemented in logic circuits integrated into individual memory array elements in which the numerical weight data are stored. In this regard, a ternary computation circuit (TCC) includes a memory circuit integrated with a logic circuit. A memory array including TCCs performs a plurality of parallel operations (e.g., column or row elements) and determines a popcount. A TCC array in which logic circuits in columns or rows employ a single read-enable signal can reduce routing complexity and congestion of a metal layer in a semiconductor device.

First claim

What is claimed is:

1. A ternary computation circuit (TCC), comprising:
a read-enable input configured to receive a read-enable signal;
a plurality of inputs configured to receive a plurality of input signals indicating a ternary input value;
a ternary output;
a memory bit cell circuit configured to store a weight data and a complement weight data complementary to the weight data; and
a ternary multiply circuit configured to multiply the ternary input value and the weight data in response to the read-enable signal indicating an active state, the ternary multiply circuit comprising:
a first control circuit configured to couple at least one of a first input signal and a second input signal among the plurality of input signals to a first signal node to generate a first product input signal based on the weight data;
a second control circuit configured to couple at least one of a third input signal and a fourth input signal among the plurality of input signals to a second signal node to generate a second product input signal based on the weight data; and
a product circuit configured to couple the first signal node to the ternary output in response to the read-enable signal and couple the second signal node to the ternary output in response to the read-enable signal to generate a ternary product signal on the ternary output based on the first product input signal and the second product input signal;
wherein the product circuit comprises:
a first pass-gate transistor of a first type coupled to the first signal node;
a second pass-gate transistor of the first type coupled to the second signal node; and
a gate of the first pass-gate transistor and a gate of the second pass-gate transistor coupled to each other and configured to receive the read-enable signal.

2. The TCC of claim 1 , wherein:
the product circuit is configured to generate the ternary product signal in response to a first voltage on the read-enable input indicating the read-enable signal is in the active state.

3. The TCC of claim 1 , wherein:
the TCC does not comprise a second read-enable input configured to receive a second read-enable signal comprising a voltage different than a voltage of the read-enable signal to cause the product circuit to generate the ternary product signal on the ternary output.

4. The TCC of claim 1 , wherein:
the first control circuit is configured to couple the first input signal and the second input signal among the plurality of input signals to the first signal node; and
the second control circuit is configured to couple the third input signal and the fourth input signal among the plurality of input signals to the second signal node.

5. The TCC of claim 4 , wherein:
the first control circuit comprises a first transistor of either an N-type or a P-type serially coupled to a second transistor of a same type as the first transistor at the first signal node; and
the second control circuit comprises a third transistor of either the N-type or the P-type serially coupled to a fourth transistor of a same type as the third transistor at the second signal node.

6. The TCC of claim 1 , wherein:
the first control circuit is configured to couple only one of the first input signal and the second input signal among the plurality of input signals to the first signal node; and
the second control circuit is configured to couple only one of the third input signal and the fourth input signal among the plurality of input signals to the second signal node.

7. The TCC of claim 6 , wherein:
the first control circuit comprises a first transistor of either an N-type or a P-type serially coupled to a second transistor of a type opposite to the first transistor at the first signal node; and
the second control circuit comprises a third transistor of either the N-type or the P-type serially coupled to a fourth transistor of a type opposite to the third transistor at the second signal node.

8. The TCC of claim 1 , further comprising:
a data line of the memory bit cell circuit on which the weight data is carried to the first control circuit; and
a complement data line of the memory bit cell circuit on which the complement weight data is carried to the second control circuit.

9. The TCC of claim 8 , wherein:
the first control circuit comprises a first transistor serially coupled to a second transistor at the first signal node;
the second control circuit comprises a third transistor serially coupled to a fourth transistor at the second signal node;
a gate of the first transistor of the first control circuit and a gate of the second transistor of the first control circuit are coupled to the data line; and
a gate of the third transistor of the second control circuit and a gate of the fourth transistor of the second control circuit are coupled to the complement data line.

10. The TCC of claim 1 , wherein:
the first control circuit further comprises:
a first P-type transistor comprising:
a first source/drain region coupled to the first signal node of the first control circuit;
a gate coupled to a data line of the memory bit cell circuit; and
a second source/drain region coupled to the first input signal among the plurality of input signals indicating the ternary input value; and

a first N-type transistor comprising:
a first source/drain region coupled to the first signal node of the first control circuit;
a gate coupled to the data line of the memory bit cell circuit; and
a second source/drain region coupled to the second input signal among the plurality of input signals indicating the ternary input value; and

the second control circuit further comprises:
a second P-type transistor comprising:
a first source/drain region coupled to the second signal node of the second control circuit;
a gate coupled to a complement data line of the memory bit cell circuit; and
a second source/drain region coupled to the third input signal among the plurality of input signals indicating the ternary input value; and

a second N-type transistor comprising:
a first source/drain region coupled to the second signal node of the second control circuit;
a gate coupled to the complement data line of the memory bit cell circuit; and
a second source/drain region coupled to the fourth input signal among the plurality of input signals indicating the ternary input value.

11. The TCC of claim 1 , wherein:
the first pass-gate transistor further comprises:
a first source/drain region coupled to the first signal node; and
a second source/drain region coupled to the ternary output; and

the second pass-gate transistor further comprises:
a first source/drain region coupled to the second signal node; and
a second source/drain region coupled to the ternary output.

12. The TCC of claim 11 , wherein:
the second source/drain region of the first pass-gate transistor is coupled to the second source/drain region of the second pass-gate transistor; and
the ternary product signal comprises an analog signal.

13. The TCC of claim 11 , wherein:
the second source/drain region of the first pass-gate transistor is coupled to a first read bit line;
the second source/drain region of the second pass-gate transistor is coupled to a second read bit line; and
the ternary product signal is generated as a two-bit binary value on the first read bit line and the second read bit line.

14. The TCC of claim 1 , wherein:
the ternary multiply circuit is further configured to multiply the ternary input value and the weight data by binary operations on a first binary input signal among the plurality of input signals, a second binary input signal among the

Assignees

• Qualcomm Inc

Inventors

• Li Xia

Classifications

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title