Super block management method and apparatus

Patent metadata

Field	Value
Publication number	US-12566561-B2
Application number	US-202418584329-A
Country	US
Kind code	B2
Filing date	Feb 22, 2024
Priority date	Aug 23, 2021
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

This application discloses a super block management method and apparatus. An example method includes: obtaining a parameter of a memory and a type of target data, where the target data is data to be written into the memory; configuring a capacity of a section in a file system based on at least one of the type of the target data or the parameter of the memory, where the configured capacity of the section matches a capacity of a super block in the memory; and managing, based on the configured capacity of the section, a logical address space corresponding to the memory.

First claim

What is claimed is:

1 . A method for super block management, wherein the method comprises:
obtaining a parameter of a memory and a type of target data, wherein the target data is data to be written into the memory; configuring a capacity of a section in a file system based on at least one of the type of the target data or the parameter of the memory, wherein the file system is separate from the memory, the section is a logical address space management unit in the file system, and the configured capacity of the section matches a capacity of a super block in the memory, wherein the memory comprises at least one die, and each of the at least one die comprises at least one physical block; and the super block is a management unit in the memory, the super block comprises at least one physical block, and each of the at least one physical block is located on a different die, and wherein the parameter comprises a quantity of idle super blocks in the memory and a quantity of dies; and at least one of the following is true:
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; or
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; and
managing, based on the configured capacity of the section, a logical address space corresponding to the memory.

2 . The method according to claim 1 , wherein the managing, based on the configured capacity of the section, a logical address space corresponding to the memory comprises:
determining E configured sections from the logical address space corresponding to the memory, wherein the E configured sections respectively correspond to E super blocks in the memory; and indicating a processor to reclaim data in the E super blocks to F idle super blocks, wherein E is greater than F, and E and F are positive integers.

3 . The method according to claim 1 , wherein the managing, based on the configured capacity of the section, a logical address space corresponding to the memory comprises:
determining K configured sections from the logical address space corresponding to the memory, wherein the K configured sections respectively correspond to K super blocks in the memory; and indicating the memory to write the target data into the K super blocks, wherein K is a positive integer.

4 . A device, comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one memory stores program instructions for execution by the at least one processor to cause the device to perform operations comprising:
obtaining a parameter of the at least one memory and a type of target data, wherein the target data is data to be written into the at least one memory; configuring a capacity of a section in a file system based on at least one of the type of the target data or the parameter of the at least one memory, wherein the file system is separate from the at least one memory, the section is a logical address space management unit in the file system, and the configured capacity of the section matches a capacity of a super block in the at least one memory, wherein the memory comprises at least one die, and each of the at least one die comprises at least one physical block; and the super block is a management unit in the memory, the super block comprises at least one physical block, and each of the at least one physical block is located on a different die, and wherein the parameter comprises a quantity of idle super blocks in the memory and a quantity of dies; and at least one of the following is true:
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; or
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; and
managing, based on the configured capacity of the section, a logical address space corresponding to the at least one memory.

5 . The device according to claim 4 , wherein managing, based on the configured capacity of the section, the logical address space corresponding to the at least one memory comprises:
determining E configured sections from the logical address space corresponding to the at least one memory, wherein the E configured sections respectively correspond to E super blocks in the at least one memory; and indicating the at least one processor to reclaim data in the E super blocks to F idle super blocks, wherein E is greater than F, and E and F are positive integers.

6 . The device according to claim 4 , wherein managing, based on the configured capacity of the section, the logical address space corresponding to the at least one memory comprises:
determining K configured sections from the logical address space corresponding to the at least one memory, wherein the K configured sections respectively correspond to K super blocks in the at least one memory; and indicating the at least one memory to write the target data into the K super blocks, wherein K is a positive integer.

7 . A chip system, wherein the chip system comprises at least one processor, at least one memory, and an interface circuit; the at least one memory, the interface circuit, and the at least one processor are connected to each other through a line; and the at least one memory stores program instructions for execution by the at least one processor to cause the chip system to perform operations comprising:
obtaining a parameter of the at least one memory and a type of target data, wherein the target data is data to be written into the at least one memory; configuring a capacity of a section in a file system based on at least one of the type of the target data or the parameter of the at least one memory, wherein the file system is separate from the at least one memory, the section is a logical address space management unit in the file system, and the configured capacity of the section matches a capacity of a super block in the at least one memory, wherein the memory comprises at least one die, and each of the at least one die comprises at least one physical block; and the super block is a management unit in the memory, the super block comprises at least one physical block, and each of the at least one physical block is located on a different die, and wherein the parameter comprises a quantity of idle super blocks in the memory and a quantity of dies; and at least one of the following is true:
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; or
when the quantity of idle super blocks is less than or equal to a preset quantity, a quantity of physical blocks, in the memory, corresponding to the configured capacity of the section is less than the quantity of dies; and
managing, based on the configured capacity of the section, a logical address space corresponding to the at least one memory.

8 . The chip system according to claim 7 , wherein the managing, based on the configured capacity of the section, a logical address space corresponding to the at least one memory comprises:
determining E configured sections from the logical address space corresponding to the at least one

Assignees

• Huawei Tech Co Ltd

Inventors

• Qiu Laibin
• Fang Wei
• Miao Xie
• Zhao Hongjiang
• Qiu Jie

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/0607

  Interleaved addressing · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title