Method and system for providing programmable microcontroller unit (MCU) using two-phase configuration process

Patent metadata

Field	Value
Publication number	US-12566417-B2
Application number	US-202418608916-A
Country	US
Kind code	B2
Filing date	Mar 18, 2024
Priority date	May 12, 2017
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

One embodiment of the present invention discloses a two-phase configuration process (“TCP”) to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

First claim

What is claimed is:

1 . A semiconductor apparatus containing at least one programmable device for providing digital network communication, comprising:
a field-programmable gate array (“FPGA”), configured by a stream of FPGA configuration data during a phase I configuration, containing a plurality of configurable logic blocks (“LBs”) able to be selectively programmed to perform one or more user-defined logic function; and a configurable microcontroller (“CM”), configured by a stream of CM configuration data during a phase II configuration, coupled to the FPGA and configured to be programmed to handle a first interface protocol of inter-integrated circuit (“I2C”) and second interface protocol of two-wire interface (“TWI”) for facilitating communication between a plurality of input and output (“I/O”) ports and an external device in accordance with interface programming microcode.

2 . The apparatus of claim 1 , wherein the CM is configured to be programmable to one or more interface blocks for handling I/O interface protocol of serial peripheral interface (“SPI”) for facilitating I/O interface.

3 . The apparatus of claim 1 , further comprising a processor configured to communicate with a host central processing unit (“CPU”) based on a set of predefined instruction code.

4 . The apparatus of claim 1 , further comprising a memory coupled to the FPGA and configured to store predefined programming microcode downloadable from a cloud system.

5 . The apparatus of claim 4 , wherein the memory includes a flash memory for storing downloaded bitmaps from a remote location via a communication network.

6 . The apparatus of claim 4 , wherein the memory includes a static random-access memory (“SRAM”) for storing data.

7 . The apparatus of claim 4 , wherein at least a portion of the memory is configured to store information indicating one of a single port and a dual port operation in accordance with memory programmable-code.

8 . The apparatus of claim 1 , wherein the plurality of I/O ports is configured to couple to multiple external devices.

9 . The apparatus of claim 1 , wherein the CM includes multiple programmable interfaces configured to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with programming microcode.

10 . The apparatus of claim 1 , wherein the CM is configured to be programmable to one or more interface blocks for handling I/O interface protocol of universal asynchronous receiver-transmitter (“UART”) for facilitating I/O interface.

11 . The apparatus of claim 1 , wherein the CM is configured to be programmable to one or more interface blocks for handling I/O interface protocol of Integer (“Int”) interface protocol to facilitate communication between the plurality of I/O ports and one or more external devices in accordance with a set of predefined programming microcode.

12 . The apparatus of claim 1 , wherein the CM is configured to be programmable to one or more interface blocks for handling I/O interface protocol of two-wire interface (“TWI”) protocol to facilitate communication.

13 . The apparatus of claim 1 , wherein the CM is configured to be programmable to one or more interface blocks for handling I/O interface protocol of Timer interface protocol to facilitate communication.

14 . A method for providing network communication utilizing at least one programmable device comprising:
obtaining a first configuration bit stream from a first memory; configuring a plurality of configurable logic blocks (“LBs”) in a field-programmable gate array (“FPGA”) based on the first configuration bit stream during a phase I configuration for performing one or more user-defined logic function; obtaining a second configuration bit stream from a second memory; and programming a configurable microcontroller (“CM”) in response to the second configuration bit stream during a phase II configuration to handle a first interface protocol of inter-integrated circuit (“I2C”) and second interface protocol of two-wire interface (“TWI”) for facilitating communication between input and output (“I/O”) ports of the CM and one or more external devices.

15 . The method of claim 14 , further comprising programming the CM to handle I/O interface protocol of serial peripheral interface (“SPI”) for facilitating I/O interface.

16 . The method of claim 14 , further comprising programming the CM to handle I/O interface protocol of universal asynchronous receiver-transmitter (“UART”) for facilitating I/O interface.

17 . The method of claim 14 , wherein configuring FPGA further includes configuring a portion of the FPGA in accordance with first configuration data retrieved from a first configuration memory to behave as a configurable MCU emulating a processor function.

18 . The method of claim 14 , wherein programming the CM further includes configuring the CM in response to a second configuration data retrieved from a second configuration memory to perform at least one user-defined microcontroller unit (“MCU”) function.

19 . The method of claim 14 , further comprising receiving first configuration data from a first external storage location via a communication bus.

20 . The method of claim 14 , further comprising storing the first configuration data in the first configuration memory for configuring FPGA to contain a configurable MCU.

21 . An apparatus for providing network communication utilizing at least one programmable device comprising:
means for obtaining a first configuration bit stream from a first memory; means for configuring a plurality of configurable logic blocks (“LBs”) in a field-programmable gate array (“FPGA”) based on the first configuration bit stream during a phase I configuration for performing one or more user-defined logic function; means for obtaining a second configuration bit stream from a second memory; and means for programming a configurable microcontroller (“CM”) in response to the second configuration bit stream during a phase II configuration to handle a first interface protocol of inter-integrated circuit (“I2C”) and second interface protocol of two-wire interface (“TWI”) for facilitating communication between input and output (“I/O”) ports of the CM and one or more external devices.

22 . The apparatus of claim 21 , further comprising means for programming the CM to handle I/O interface protocol of serial peripheral interface (“SPI”) for facilitating I/O interface.

Assignees

• Gowin Semiconductor Corp

Inventors

• Zhu Jinghui

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G05B2219/25257

  Microcontroller · CPC title

• G06F2213/0016

  Inter-integrated circuit (I2C) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G05B19/0426

  Programming the control sequence · CPC title