High performance context switching for virtualized FPGA accelerators

Patent metadata

Field	Value
Publication number	US-10540200-B2
Application number	US-201715809940-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Nov 10, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

First claim

What is claimed is:

1. A hardware context manager in a field programmable gate array (FPGA) device, comprising:
configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions;
context management logic coupled with the configuration logic, wherein the context management logic is configured to:
save a first context corresponding to the target configuration by:
retrieving first state information from the set of one or more programming regions, wherein the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory, and

restore the first context by:
transferring the first state information from the context memory to the one or more programming regions, and
causing the configuration logic to program the one or more programming regions based on the configuration data; and

scheduling logic coupled with the configuration logic and the context management logic, wherein the scheduling logic is configured to control timing of saving the first context based on a sequence of tasks to be executed in the one or more programming regions.

2. The hardware context manager of claim 1 , wherein the context memory comprises block random access memory (BRAM) in the FPGA device, dynamic random access memory (DRAM) located on a carrier card of the FPGA device, and memory external to the carrier card.

3. The hardware context manager of claim 1 , wherein the context management logic comprises allocation logic configured to allocate context memory for the first state information based on an expected access frequency of the first state information.

4. The hardware context manager of claim 1 , wherein memory in the one or more programming regions is connected in a scan chain, and wherein the context management logic is configured to restore the first context simultaneously with saving a second context by shifting the first state information into the scan chain while shifting second state information for the second context out of the scan chain.

5. The hardware context manager of claim 1 , wherein the configuration logic and the context management logic are located on the same FPGA die as the one or more programming regions.

6. The hardware context manager of claim 1 , wherein the scheduling logic is configured to control timing of restoring the first context by the context management logic based on the sequence of tasks to be executed in the one or more programming regions.

7. The hardware context manager of claim 6 , wherein the scheduling logic is configured to cause the context management logic to save the first context in response to determining that execution of a task in the one or more programming regions has reached a checkpoint.

8. The hardware context manager of claim 1 , further comprising:
a bidirectional configuration port coupled with the configuration logic and coupled with the context management logic, wherein the bidirectional configuration port is configured to:
transmit the configuration data and the first state information to the one or more programming regions, and
receive the first state information from the one or more programming regions.

9. A method, comprising:
programming one or more programming regions in a field programmable gate array (FPGA) device based on configuration data for implementing a target configuration of the one or more programming regions;
saving a first context corresponding to the target configuration by transferring first state information from the set of one or more programming regions to a context memory, wherein the first state information is generated based on the target configuration; and
restoring the first context by:
transferring the first state information from the context memory to the one or more programming regions, and
reprogramming the one or more programming regions based on the configuration data; and

in the FPGA device, controlling timing of saving the first context based on a sequence of tasks to be executed in the one or more programming regions.

10. The method of claim 9 , wherein the reprogramming of the one or more programming regions and the transferring of the first state information from the context memory to the one or more programming regions are performed in response to a command requesting the restoring of the first context, and wherein the reprogramming is performed prior to executing a task in the one or more programming regions.

11. The method of claim 9 , wherein memory in the one or more programming regions is connected in a scan chain, and wherein the transferring the first state information from the context memory to the one or more programming regions comprises:
enabling the scan chain, and
shifting the first state information into the scan chain while simultaneously shifting second state information out of the scan chain.

12. The method of claim 9 , further comprising:
in response to receiving from a host device a request to execute a task in the target configuration of the one or more programming regions, scheduling the programming; and
controlling the timing of the saving of the first context and the restoring of the first context based on a sequence of tasks assigned for execution in the one or more programming regions.

13. The method of claim 9 , wherein the context memory comprises one or more of block random access memory (BRAM) in the FPGA device, dynamic random access memory (DRAM) located outside the FPGA device and on a carrier card of the FPGA device, and memory external to the carrier card, wherein the method further comprises allocating context memory for the first state information based on an expected access frequency of the first state information.

14. The method of claim 9 , wherein the saving of the first context is performed in response to determining that execution of a task in the one or more programming regions has reached a checkpoint.

15. A computing system, comprising:
one or more programming regions in a field programmable gate array (FPGA) device;
a context memory;
a hardware context manager in the FPGA device, comprising:
configuration logic configured to program the one or more programming regions based on configuration data for implementing a target configuration of the one or more programming regions; and
context management logic coupled with the configuration logic, wherein the context management logic is configured to:
save a first context corresponding to the target configuration by:
retrieving state information from the set of one or more programming regions, wherein the state information is generated based on the target configuration, and
storing the retrieved state information in the context memory, and

restore the first context by:
transferring the state information from the context memory to the one or more programming regions, and
causing the configuration logic to program the one or more programming regions based on the configuration data; and

scheduling logic coupled with the configuration logic and the context management logic, wherein the scheduling logic is configured to control timing of saving the first context based on a sequence of tasks to be executed in the one or more programming regions.

16. The computing system of claim 15 , wherein the hardware context manager comprises dedicated logic circuitry on the same die as the one or more programming regions.

17. The computing system of claim 15 , wherein the har

Assignees

• Advanced Micro Devices Inc

Inventors

• Cheng Kevin Y
• Roberts David A
• Brantley William C

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/461 Primary

  Saving or restoring of program or task context · CPC title