Display substrate, preparing method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-12563922-B2
Application number	US-202218016869-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Feb 25, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A display substrate, a preparing method therefor, and a display apparatus are disclosed. The display substrate includes a display region ( 100 ), the display region ( 100 ) includes a plurality of sub-pixels, at least one sub-pixel includes a circuit unit disposed on the base substrate ( 101 ), the circuit unit at least includes a pixel drive circuit and a data signal line ( 60 ), the pixel drive circuit is connected with the data signal line ( 60 ); the base substrate ( 101 ) includes a base substrate conductive layer disposed between the first flexible layer ( 101 A) and the second flexible layer ( 101 C), the base substrate conductive layer at least includes a data fan-out line ( 70 ), and the data signal line ( 60 ) is connected with the data fan-out line ( 70 ) through a lapping via (DV 1 ).

First claim

The invention claimed is:

1 . A display substrate, comprising a display region, wherein, the display region comprises a plurality of sub-pixels, at least one sub-pixel comprises a circuit unit disposed on a base substrate, the circuit unit comprises a pixel drive circuit and a data signal line, the pixel drive circuit is connected with the data signal line; the base substrate comprises a first flexible layer, a second flexible layer and a base substrate conductive layer disposed between the first flexible layer and the second flexible layer, the base substrate conductive layer of the at least one sub-pixel comprises a data fan-out line, and the data signal line is connected with the data fan-out line through a lapping via,
wherein the circuit unit comprises a lapping electrode connected with the data fan-out line through a first lapping via, and the data signal line is connected with the lapping electrode through a second lapping via,
wherein the at least one sub-pixel further comprises a light emitting device disposed at a side of the circuit unit away from the base substrate, the light emitting device comprises an anode, and the anode is connected with the pixel drive circuit through an anode via, and an orthographic projection of the first lapping via in a plane of the display substrate is not overlapped with an orthographic projection of the anode via in the plane of the display substrate,
wherein the light emitting device further comprises a pixel definition layer on which a pixel opening is provided, and the pixel opening exposes the anode; an orthographic projection of the pixel opening in the plane of the display substrate is not overlapped with the orthographic projection of the anode via in the plane of the display substrate, and
wherein the orthographic projection of the pixel opening in the plane of the display substrate is not overlapped with an orthographic projection of the first lapping via in the plane of the display substrate, a distance between an edge of a side of the pixel opening close to the first lapping via and an edge of a side of the first lapping via close to the pixel opening is greater than or equal to 2.5 μm, a distance between an edge of a side of the pixel opening close to the anode via and an edge of a side of the anode via close to the pixel opening is greater than or equal to 3.0 μm, a distance between an edge of a side of the first lapping via close to the anode via and an edge of a side of the anode via close to the first lapping via is greater than or equal to 2.5 μm.

2 . The display substrate according to claim 1 , wherein, the display region comprises a plurality of pixel rows sequentially disposed along a second direction, each pixel row comprises a plurality of sub-pixels sequentially disposed along a first direction, the second direction is an extension direction of the data signal line, the first direction intersects with the second direction; the display region is provided with a lapping zone at a middle portion in the second direction, the lapping zone comprises at least one pixel row, and the lapping via is disposed in at least one sub-pixel of the lapping zone.

3 . The display substrate according to claim 2 , wherein, lapping vias are disposed in a plurality of sub-pixels of one pixel row in the lapping zone, or lapping vias are disposed in a plurality of sub-pixels of a plurality of pixel rows in the lapping zone, and at least part of data signal lines are connected with data fan-out lines through the lapping vias.

4 . The display substrate according to claim 3 , wherein, in a plane perpendicular to the display substrate, the circuit unit comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are sequentially disposed on the base substrate; the semiconductor layer comprises active layers of a plurality of transistors, the first conductive layer comprises gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer comprises a second plate of the storage capacitor, the third conductive layer comprises the data signal line, and the fourth conductive layer comprises an anode connection electrode.

5 . The display substrate according to claim 2 , wherein, in a plane perpendicular to the display substrate, the circuit unit comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are sequentially disposed on the base substrate; the semiconductor layer comprises active layers of a plurality of transistors, the first conductive layer comprises gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer comprises a second plate of the storage capacitor, the third conductive layer comprises the data signal line, and the fourth conductive layer comprises an anode connection electrode.

6 . The display substrate according to claim 1 , wherein, the base substrate conductive layer further comprises a power supply electrode disposed in a region other than the data fan-out line, and the power supply electrode is in an entire surface structure or a mesh structure.

7 . The display substrate according to claim 1 , wherein, in a plane perpendicular to the display substrate, the circuit unit comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer that are sequentially disposed on the base substrate; the semiconductor layer comprises active layers of a plurality of transistors, the first conductive layer comprises gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer comprises a second plate of the storage capacitor, the third conductive layer comprises the data signal line, and the fourth conductive layer at least comprises an anode connection electrode.

8 . The display substrate according to claim 7 , wherein, the second conductive layer further comprises the lapping electrode.

9 . The display substrate according to claim 1 , wherein, in a plane perpendicular to the display substrate, the pixel drive circuit comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer that are sequentially disposed on the base substrate, the first semiconductor layer comprises active layers of a plurality of low temperature polysilicon transistors, the first conductive layer comprises gate electrodes of a plurality of low temperature polysilicon transistors and a first plate of a storage capacitor, the second conductive layer comprises lower gate electrodes of oxide transistors and a second plate of the storage capacitor, the second semiconductor layer comprises active layers of oxide transistors, the third conductive layer comprises upper gate electrodes of oxide transistors, the fourth conductive layer comprises the data signal line, and the fifth conductive layer comprises an anode connection electrode.

10 . The display substrate according to claim 9 , wherein, the third conductive layer comprises the lapping electrode.

11 . The display substrate according to claim 10 , wherein, the base substrate conductive layer further comprises a shield layer, and an orthographic projection of an active layer of a low temperature polysilicon transistor in a plane of the display substrate is within a range of an orthographic projection of the shield layer in the plane of the display substrate.

12 . A display

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Ding Xiaoqi
• Liu Changchang
• Tian Xuewei
• Liu Ke
• Fang Fei
• Chen Liqiang
• Shi Ling
• Li Shuo
• Cui Guoyi
• Yang Xinlei

Classifications

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K2102/311

  Flexible OLED · CPC title

• H10K77/111

  Flexible substrates · CPC title

• H10K59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title