Display panel and method for manufacturing the same, and display apparatus

Patent metadata

Field	Value
Publication number	US-12563898-B2
Application number	US-202117914686-A
Country	US
Kind code	B2
Filing date	Nov 18, 2021
Priority date	May 21, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A display panel includes a plurality of sub-pixels, a sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes at least a driving transistor and a storage capacitor. The display panel further includes a substrate, and a first gate conductive layer, a semiconductor layer and a second gate conductive layer that are disposed on the substrate. The first gate conductive layer includes a first electrode plate of the storage capacitor. The semiconductor layer includes an active layer pattern of the driving transistor. At least part of the active layer pattern of the driving transistor and at least part of the first electrode plate are disposed in a same layer. The second gate conductive layer includes a second electrode plate of the storage capacitor and a gate electrode of a driving transistor electrically connected to the second electrode plate.

First claim

What is claimed is:

1 . A display panel comprising a plurality of sub-pixels, a sub-pixel including a pixel driving circuit, and the pixel driving circuit including at least a driving transistor and a storage capacitor; the display panel further comprising:
a substrate; a first gate conductive layer disposed on the substrate and including a first electrode plate of the storage capacitor; a semiconductor layer disposed on the substrate and including an active layer pattern of the driving transistor; at least part of the active layer pattern of the driving transistor and at least part of the first electrode plate being disposed in a same layer; and a second gate conductive layer disposed on a side of the first gate conductive layer and the semiconductor layer away from the substrate, and including a second electrode plate of the storage capacitor, and a gate of the driving transistor electrically connected to the second electrode plate; wherein the pixel driving circuit further includes a first initialization transistor; the semiconductor layer further includes an active layer pattern of the first initialization transistor; at least part of the active layer pattern of the first initialization transistor and the at least part of the first electrode plate are disposed in a same layer, and the active layer pattern of the first initialization transistor is in direct contact with and electrically connected to the first electrode plate; and the second gate conductive layer further includes a gate of the first initialization transistor.

2 . The display panel according to claim 1 , wherein the first electrode plate is in direct contact with and electrically connected to the active layer pattern of the driving transistor.

3 . The display panel according to claim 2 , wherein an orthogonal projection of the first electrode plate on the substrate partially overlaps with an orthogonal projection of the active layer pattern of the driving transistor on the substrate.

4 . The display panel according to claim 3 , wherein a portion, whose orthogonal projection on the substrate overlapping with the orthogonal projection of the active layer pattern of the driving transistor on the substrate, of the first electrode plate is located on a side of the active layer pattern of the driving transistor proximate to the substrate.

5 . The display panel according to claim 3 , wherein a portion, whose orthogonal projection on the substrate overlapping with the orthogonal projection of the active layer pattern of the driving transistor on the substrate, of the first electrode plate is located on a side of the active layer pattern of the driving transistor away from the substrate.

6 . The display panel according to claim 1 , wherein an orthogonal projection of the first electrode plate on the substrate partially overlaps with an orthogonal projection of the active layer pattern of the first initialization transistor on the substrate.

7 . The display panel according to claim 6 , wherein a portion, whose orthogonal projection on the substrate overlapping with the orthogonal projection of the active layer pattern of the first initialization transistor on the substrate, of the first electrode plate is located on a side of the active layer pattern of the first initialization transistor proximate to the substrate.

8 . The display panel according to claim 1 , further comprising:
a source-drain conductive layer disposed on a side of the second gate conductive layer away from the substrate; the source-drain conductive layer including a first connection pattern; a first insulating layer disposed between the second gate conductive layer and both the semiconductor layer and the first gate conductive layer; and a second insulating layer disposed between the second gate conductive layer and the source-drain conductive layer; the second insulating layer being provided with a plurality of first via holes therein; wherein the first connection pattern is electrically connected to the second electrode plate through at least one first via hole.

9 . The display panel according to claim 8 , wherein the pixel driving circuit further includes a data writing transistor and a second initialization transistor; the semiconductor layer further includes: an active layer pattern of the data writing transistor including a source contact region and a drain contact region, and an active layer pattern of the second initialization transistor including a source contact region and a drain contact region; the first insulating layer and the second insulating layer are provided with a plurality of second via holes therein; and
the first connection pattern is electrically connected to the source contact region or the drain contact region of the active layer pattern of the data writing transistor through at least one second via hole, and the first connection pattern is electrically connected to the source contact region or the drain contact region of the active layer pattern of the second initialization transistor through another at least one second via hole.

10 . The display panel according to claim 8 , further comprising a light-emitting device; wherein the first insulating layer and the second insulating layer are provided with a plurality of third via holes therein, and the active layer pattern of the first initialization transistor includes a source contact region and a drain contact region;
the source-drain conductive layer further includes: a second connection pattern, the second connection pattern is electrically connected to the source contact region or the drain contact region of the active layer pattern of the first initialization transistor through at least one third via hole; the second connection pattern is configured to be electrically connected to the light-emitting device of the display panel.

11 . The display panel according to claim 8 , wherein the pixel driving circuit further includes a control transistor, the semiconductor layer further includes an active layer pattern of the control transistor including a source contact region and a drain contact region, the active layer pattern of the driving transistor includes a source contact region and a drain contact region, and the first insulating layer and the second insulating layer are provided with a plurality of fourth via holes; and
the source-drain conductive layer further includes: a third connection pattern, the third connection pattern is electrically connected to the source contact region or the drain contact region of the active layer pattern of the control transistor through at least one fourth via hole, and is electrically connected to the source contact region or the drain contact region of the active layer pattern of the driving transistor through another at least one fourth via hole.

12 . The display panel according to claim 8 , wherein the plurality of sub-pixels are arranged in a plurality of rows and columns, each row of sub-pixels includes sub-pixels arranged in a first direction, and each column of sub-pixels includes sub-pixels arranged in a second direction;
the source-drain conductive layer further includes voltage signal lines, data signal lines, first initialization signal lines and second initialization signal lines that each extend in the second direction; each column of sub-pixels are electrically connected to a corresponding data signal line, and at least two columns of sub-pixels are disposed between two adjacent voltage signal lines, between two adjacent first initialization signal lines, and between two adjacent second initialization signal lines; the first gate conductive layer further includes a first transition line exten

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yuan Zhidong
• Xu Pan
• Liu Jun
• Yuan Can
• Li Yongqian

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title