Wiring board, functional backplane, backlight module, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12563875-B2
Application number	US-202117927792-A
Country	US
Kind code	B2
Filing date	Dec 29, 2021
Priority date	Dec 29, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A wiring board includes a substrate, conductive pads and at least one protective layer group. The conductive pads are disposed on the substrate. The at least one protective layer group is disposed on a side of the conductive pads away from the substrate; a protective layer group includes an oxidation protective layer and a palladium alloy layer that are stacked, and the oxidation protective layer is closer to the substrate than the palladium alloy layer. A material of the oxidation protective layer includes a nickel-based alloy.

First claim

What is claimed is:

1 . A wiring board, comprising:
a substrate; conductive pads disposed on the substrate, wherein the conductive pads are configured to transmit a driving signal; a plurality of protective layer groups stacked on a side of the conductive pads away from the substrate, wherein a protective layer group in the plurality of protective layer groups includes an oxidation protective layer and a palladium alloy layer that are stacked, and the oxidation protective layer is closer to the substrate than the palladium alloy layer, wherein a material of the oxidation protective layer includes a nickel-based alloy; and a protective pad layer disposed between two adjacent protective layer groups.

2 . The wiring board according to claim 1 , wherein the nickel-based alloy includes one or more of a nickel-palladium alloy, a copper-nickel alloy, a tungsten-nickel alloy, a nickel-aluminum alloy, a nickel-titanium alloy, a nickel-vanadium alloy, a nickel-zirconium alloy, a nickel-gold alloy, a nickel-yttrium alloy, a nickel-niobium alloy, a nickel-platinum alloy, a nickel-tin alloy, a nickel-silver alloy and a nickel-tantalum alloy.

3 . The wiring board according to claim 1 , wherein a thickness of the oxidation protective layer is in a range of 0.5 μm to 1.45 μm, inclusive; and/or
a mass proportion of nickel in the material of the oxidation protective layer is in a range of 40% to 95%, inclusive.

4 . The wiring board according to claim 1 , wherein a thickness of the palladium alloy layer is in a range of 0.05 μm to 0.1 μm, inclusive; and/or
a sum of a thickness of the oxidation protective layer and the thickness of the palladium alloy layer is in a range of 0.6 μm to 1.5 μm, inclusive.

5 . The wiring board according to claim 1 , further comprising:
driving circuits disposed between the substrate and the conductive pads, wherein a conductive pad in the conductive pads is electrically connected to a driving circuit in the driving circuits.

6 . The wiring board according to claim 1 , further comprising:
traces disposed on the substrate, wherein the conductive pads are located on a side of the traces away from the substrate, and a conductive pad in the conductive pads is electrically connected to a trace in the traces.

7 . The wiring board according to claim 6 , wherein the trace includes a first adhesive layer, a first conductive layer and an electroplated metal layer that are stacked in a direction perpendicular to the substrate and directed from the substrate to the protective layer group.

8 . The wiring board according to claim 7 , wherein a material of the first adhesive layer includes one or more of a molybdenum alloy, a titanium alloy, a tungsten alloy, a nickel alloy, a molybdenum-based alloy and a nickel-based alloy; and
materials of the first conductive layer and the electroplated metal layer each include copper.

9 . The wiring board according to claim 6 , further comprising:
at least one insulating layer covering the traces, wherein the conductive pad is electrically connected to the trace through a via hole penetrating through the at least one insulating layer; or the wiring board further comprising the at least one insulating layer covering the traces, wherein the conductive pad is electrically connected to the trace through the via hole penetrating through the at least one insulating layer, and the at least one insulating layer includes a first passivation layer, a planarization layer and a second passivation layer that are stacked in a direction perpendicular to the substrate and directed from the substrate to the protective layer group.

10 . The wiring board according to claim 6 , further comprising:
a second adhesive layer disposed between the traces and the conductive pads, wherein the conductive pad is electrically connected to the trace through a portion of the second adhesive layer; or the wiring board further comprising the second adhesive layer disposed between the traces and the conductive pads, wherein the conductive pad is electrically connected to the trace through the portion of the second adhesive layer, and a material of the second adhesive layer includes one or more of a molybdenum alloy, a titanium alloy, a tungsten alloy, a nickel alloy, a molybdenum-based alloy and a nickel-based alloy.

11 . The wiring board according to claim 6 , wherein the trace includes a first adhesive layer, a first conductive layer, a second conductive layer and an anti-oxidation conductive layer that are stacked in a direction perpendicular to the substrate and directed from the substrate to the protective layer group.

12 . The wiring board according to claim 11 , wherein a material of the first adhesive layer includes one or more of a molybdenum alloy, a titanium alloy, a tungsten alloy, a nickel alloy, a molybdenum-based alloy and a nickel-based alloy;
materials of the first conductive layer and the second conductive layer each include copper; and a material of the anti-oxidation conductive layer includes one or more of molybdenum alloy, titanium alloy, tungsten alloy, nickel alloy, a molybdenum-based alloy and a nickel-based alloy.

13 . A functional backplane, comprising:
the wiring board according to claim 1 ; intermetallic compound layers and conductive connection layers, wherein an intermetallic compound layer and a conductive connection layer are stacked on the wiring board in a direction perpendicular to the substrate of the wiring board and directed from the substrate to the protective layer group; and electronic components, wherein an electronic component is electrically connected to the conductive connection layer.

14 . The functional backplane according to claim 13 , wherein the intermetallic compound layer is disposed between the conductive connection layer and the palladium alloy layer of the wiring board; or
the palladium alloy layer includes hollowed-out areas; and a portion of the intermetallic compound layer is located between the palladium alloy layer and the conductive connection layer, and another portion of the intermetallic compound layer is in contact with the oxidation protective layer of the wiring board through a hollowed-out area in the hollowed-out areas.

15 . The functional backplane according to claim 13 , further comprising: first plating layers, wherein a first plating layer is disposed between the palladium alloy layer and the intermetallic compound layer; and/or
the wiring board has a device area and a bonding area; the conductive pads include first conductive pads disposed in the device area, and second conductive pads disposed in the bonding area; and the electronic component includes: a light-emitting device bonded to a first conductive pad in the first conductive pads, and a driving circuit board bonded to a second conductive pad in the second conductive pads.

16 . A backlight module, comprising: the functional backplane according to claim 13 .

17 . A display apparatus, comprising:
a display panel; and the backlight module according to claim 16 , the display panel being disposed at a light-exit side of the backlight module.

18 . A display panel, comprising: the functional backplane according to claim 13 .

19 . A display apparatus, comprising: the display panel according to claim 18 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• He Jiayu
• Qu Yan
• Ning ce
• Li Zhengliang
• Hu hehe
• Huang Jie
• Yao Nianqi
• Zhao Kun
• Li Feifei
• Qi Qi

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10H20/857 Primary

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H05K3/34

  by soldering · CPC title