Drive backplane, method for manufacturing same, and display panel

Patent metadata

Field	Value
Publication number	US-12563835-B2
Application number	US-202218020601-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Provided is a drive backplane. The drive backplane includes: a base substrate and a circuit structure. The circuit structure includes a plurality of first thin film transistors and a plurality of second thin film transistors; wherein a first active layer of the first thin film transistor includes a first oxide layer and a second oxide layer, wherein the second oxide layer is disposed on a side of the first oxide layer away from the base substrate, a mobility of the second oxide layer is lower than a mobility of the first oxide layer, and a source and a drain of the first thin film transistor are connected to the second oxide layer; and a second active layer of the second thin film transistor includes a third oxide layer, wherein a mobility of the third oxide layer is lower than the mobility of the first oxide layer.

First claim

What is claimed is:

1 . A drive backplane, comprising a base substrate and a circuit structure disposed on a bearing surface of the base substrate, the circuit structure comprising a plurality of first thin film transistors and a plurality of second thin film transistors; wherein
a first active layer of the first thin film transistor comprises a first oxide layer and a second oxide layer which are laminated, wherein the second oxide layer is disposed on a side of the first oxide layer away from the base substrate, a mobility of the second oxide layer is lower than a mobility of the first oxide layer, and a source and a drain of the first thin film transistor are connected to the second oxide layer; and a second active layer of the second thin film transistor comprises a third oxide layer, wherein a mobility of the third oxide layer is lower than the mobility of the first oxide layer; wherein the base substrate comprises a display region and a frame region, wherein the frame region is disposed on at least one side of the display region; and the circuit structure comprises a pixel drive circuit and an optical acquisition circuit, wherein the pixel drive circuit is disposed in the display region, the pixel drive circuit comprises the first thin film transistor and the second thin film transistor, the optical acquisition circuit is disposed in the display region, and the optical acquisition circuit comprises the first thin film transistor.

2 . The drive backplane according to claim 1 , wherein the first active layer further comprises at least one fourth oxide layer, wherein the fourth oxide layer is disposed between the first oxide layer and the second oxide layer, and a mobility of the fourth oxide layer is not higher than the mobility of the first oxide layer and is not lower than the mobility of the second oxide layer.

3 . The drive backplane according to claim 1 , wherein the mobility of the first oxide layer ranges from 30 cm2/V·m to 100 cm2/V·m, and the mobility of the second oxide layer ranges from 5 cm2/V·m to 10 cm2/V·m.

4 . The drive backplane according to claim 1 , wherein a material of the first oxide layer is one of indium zinc oxide, hydrogen doped indium gallium oxide, indium tin zinc oxide, tin zinc oxide, indium gallium tin zinc oxide and crystallized indium gallium zinc oxide, and a material of the second oxide layer and a material of the third oxide layer are indium gallium zinc oxide.

5 . The drive backplane according to claim 1 , wherein the circuit structure further comprises a first light-shielding layer and a second light-shielding layer; wherein
the first light-shielding layer is disposed on a side of the first active layer close to the base substrate, and an orthographic projection of the first light-shielding layer on the bearing surface of the base substrate at least partially overlaps an orthographic projection of the first active layer on the bearing surface of the base substrate; and the second light-shielding layer is disposed on a side of the second active layer close to the base substrate, and an orthographic projection of the second light-shielding layer on the bearing surface of the base substrate at least partially overlaps with an orthographic projection of the second active layer on the bearing surface of the base substrate.

6 . The drive backplane according to claim 1 , wherein the circuit structure further comprises a gate driver, wherein the gate driver is disposed in the frame region, and the gate driver comprises the first thin film transistor.

7 . The drive backplane according to claim 1 , wherein the second oxide layer and the third oxide layer are disposed in a same layer.

8 . The drive backplane according to claim 7 , wherein a material of the second oxide layer is the same as a material of the third oxide layer.

9 . A method for manufacturing a drive backplane, comprising:
providing a base substrate; forming a first oxide layer on a bearing surface of the base substrate by a patterning process; forming a second oxide layer and a third oxide layer on the bearing surface of the base substrate by the patterning process to obtain a first active layer and a second active layer, wherein the second oxide layer is disposed on a side of the first oxide layer away from the base substrate, and a mobility of the second oxide layer and a mobility of the third oxide layer are both lower than a mobility of the first oxide layer; and forming a source, a drain and a gate on both the first active layer and the second active layer to obtain a first thin film transistor and a second thin film transistor; wherein the base substrate comprises a display region and a frame region, wherein the frame region is disposed on at least one side of the display region; and the circuit structure comprises a pixel drive circuit and an optical acquisition circuit, wherein the pixel drive circuit is disposed in the display region, the pixel drive circuit comprises the first thin film transistor and the second thin film transistor, the optical acquisition circuit is disposed in the display region, and the optical acquisition circuit comprises the first thin film transistor.

10 . The method according to claim 9 , wherein forming the second oxide layer and the third oxide layer on the bearing surface of the base substrate by the patterning process comprises:
forming an oxide material layer on the base substrate; and removing the oxide material layer in a region outside the first oxide layer and outside a region where the second active layer is to be formed on the base substrate, to form the second oxide layer and the third oxide layer.

11 . A display panel, comprising a drive backplane, wherein the drive backplane comprises:
a base substrate and a circuit structure disposed on a bearing surface of the base substrate, the circuit structure comprising a plurality of first thin film transistors and a plurality of second thin film transistors; wherein a first active layer of the first thin film transistor comprises a first oxide layer and a second oxide layer which are laminated, wherein the second oxide layer is disposed on a side of the first oxide layer away from the base substrate, a mobility of the second oxide layer is lower than a mobility of the first oxide layer, and a source and a drain of the first thin film transistor are connected to the second oxide layer; and a second active layer of the second thin film transistor comprises a third oxide layer, wherein a mobility of the third oxide layer is lower than the mobility of the first oxide layer; wherein the base substrate comprises a display region and a frame region, wherein the frame region is disposed on at least one side of the display region; and the circuit structure comprises a pixel drive circuit and an optical acquisition circuit, wherein the pixel drive circuit is disposed in the display region, the pixel drive circuit comprises the first thin film transistor and the second thin film transistor, the optical acquisition circuit is disposed in the display region, and the optical acquisition circuit comprises the first thin film transistor.

12 . The display panel according to claim 11 , wherein a material of the first oxide layer is one of indium zinc oxide, hydrogen doped indium gallium oxide, indium tin zinc oxide, tin zinc oxide, indium gallium tin zinc oxide and crystallized indium gallium zinc oxide, and a material of the second oxide layer and a material of the third oxide layer are indium gallium zinc oxide.

13 . The display panel according to claim 11 , wherein the circuit structure further comprises a first light-shielding layer and a second light-shi

Assignees

• Boe Technology Group Co Ltd

Inventors

• Tian Hongwei
• Niu Yanan
• Wang Jing
• Li Ran
• Tian Xueyan
• Liu Zheng
• Liu Libin
• Shi Shiming

Classifications

• H10D86/0221 Primary

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title