Active matrix substrate and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-11695016-B2
Application number	US-202117364939-A
Country	US
Kind code	B2
Filing date	Jul 1, 2021
Priority date	Jul 6, 2020
Publication date	Jul 4, 2023
Grant date	Jul 4, 2023

Abstract

An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

First claim

The invention claimed is:

1. An active matrix substrate having a display region including a plurality of pixel areas and a non-display region arranged around the display region, the active matrix substrate comprising:
a substrate; and
a plurality of oxide semiconductor TFTs supported on the substrate and provided in the display region or the non-display region, each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer and a gate electrode arranged on a part of the oxide semiconductor layer with a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, wherein
the oxide semiconductor layer has a first region covered with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode,
a first TFT and a second TFT are included in the plurality of oxide semiconductor TFTs,
in the first TFT, in at least a part of the first region of the oxide semiconductor layer, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film arranged on the high mobility oxide semiconductor film and having a relatively lower mobility than the high mobility oxide semiconductor film is provided,
in the second TFT, in the first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided and another oxide semiconductor film is not provided, and
in the first region in the second TFT, the low mobility oxide semiconductor film is provided and the highest mobility oxide semiconductor film is not provided.

2. The active matrix substrate according to claim 1 ,
wherein in the first region of the oxide semiconductor layer of the first TFT, another oxide semiconductor film having a lower mobility than the high mobility oxide semiconductor film between the high mobility oxide semiconductor film and the substrate is further provided, and
in the first region of the second TFT, another oxide semiconductor film is not provided.

3. The active matrix substrate according to claim 1 , the active matrix substrate further comprising:
a plurality of pixel TFTs each arranged in the plurality of pixel areas; and
a peripheral circuit arranged in the non-display region,
wherein the peripheral circuit includes the first TFT, and
each of the plurality of pixel TFTs is the second TFT.

4. The active matrix substrate according to claim 1 , the active matrix substrate further comprising:
a gate drive circuit and a Source Shared Driving (SSD), circuit arranged in the non-display region,
wherein the SSD circuit includes the first TFT, and
the gate drive circuit includes the second TFT.

5. The active matrix substrate according to claim 1 ,
wherein in each of the plurality of pixel areas, a pixel circuit including a selection TFT, a drive TFT, and a capacitance element is provided,
the selection TFT is the first TFT, and
the drive TFT is the second TFT.

6. The active matrix substrate according to claim 1 , the active matrix substrate further comprising:
a plurality of pixel circuits, each of the plurality of pixel circuits is arranged in each of the plurality of pixel areas and includes a selection TFT, a drive TFT, and a capacitance element; and
a gate drive circuit arranged in the non-display region,
wherein the gate drive circuit includes the first TFT, and
the drive TFT is the second TFT.

7. The active matrix substrate according to claim 1 ,
wherein each of the low mobility oxide semiconductor film and the high mobility oxide semiconductor film contains In and/or Sn, and
a sum of atomic ratios of In and Sn to all metal elements in the high mobility oxide semiconductor film is larger than a sum of atomic ratios of In and Sn to all metal elements in the low mobility oxide semiconductor film.

8. The active matrix substrate according to claim 1 ,
wherein the high mobility oxide semiconductor film contains Sn, and the low mobility oxide semiconductor film does not contain Sn or contains Sn at a lower concentration than the high mobility oxide semiconductor film.

9. The active matrix substrate according to claim 1 ,
wherein each of the plurality of oxide semiconductor TFTs further includes a source electrode and a drain electrode, and
the oxide semiconductor layer of each of the plurality of oxide semiconductor TFTs has a first contact region and a second contact region located on both sides of the first region, the first contact region is electrically connected to the source electrode, and the second contact region is electrically connected to the drain electrode.

10. The active matrix substrate according to claim 9 , the active matrix substrate further comprising:
an interlayer insulating layer covering a plurality of the gate electrodes, a plurality of the gate insulating layers, and a plurality of the oxide semiconductor layers, in the plurality of oxide semiconductor TFTs,
wherein the source electrode and the drain electrode in each of the first TFT and the second TFT are arranged on the interlayer insulating layer.

11. The active matrix substrate according to claim 9 ,
wherein in the first TFT, in the at least a part of the first region, the layered structure is provided, but in the first contact region and the second contact region, the low mobility oxide semiconductor film is provided and the high mobility oxide semiconductor film is not provided.

12. The active matrix substrate according to claim 11 ,
wherein in the first TFT, in an entire first region of the oxide semiconductor layer, the layered structure is provided.

13. The active matrix substrate according to claim 11 ,
wherein in the first TFT, in a part of the first region of the oxide semiconductor layer, the layered structure is provided, and in another part, the low mobility oxide semiconductor film is provided and the high mobility oxide semiconductor film is not provided.

14. An active matrix substrate having a display region including a plurality of pixel areas and a non-display region arranged around the display region, the active matrix substrate comprising:
a substrate; and
a plurality of oxide semiconductor TFTs supported on the substrate and provided in the display region or the non-display region, each of the plurality of oxide semiconductor TFTs includes an oxide semiconductor layer and a gate electrode arranged on a part of the oxide semiconductor layer with a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, wherein
the oxide semiconductor layer has a first region covered with the gate electrode with the gate insulating layer interposed between the oxide semiconductor layer and the gate electrode,
a first TFT and a second TFT are included in the plurality of oxide semiconductor TFTs,
in the first TFT, in at least a part of the first region of the oxide semiconductor layer, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film arranged on the high motility oxide semiconductor film and having, a relatively lower mobility than the high mobility oxide semiconductor film is provided,
in the second TFT, in the first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided an another oxide semiconductor film is not provided,
each of the plurality of oxide semiconduct

Assignees

• Sharp Kk

Inventors

• Daitoh Tohru
• Suzuki Masahiko
• Nishimiya Setsuji
• Hara Kengo
• Takahata Hitoshi
• Kikuchi Tetsuo

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title