Method for forming a field-effect transistor having a fractionally enhanced body structure

Patent metadata

Field	Value
Publication number	US-12563767-B2
Application number	US-202117490918-A
Country	US
Kind code	B2
Filing date	Sep 30, 2021
Priority date	Sep 30, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

First claim

What is claimed is:

1 . A method of forming an integrated circuit, comprising:
forming first, second and third trenches in an epitaxial layer having a first conductivity type over a substrate; forming corresponding first, second and third polysilicon field plates within the first, second and third trenches; forming a first source region between the first and second trenches, and a second source region between the second and third trenches, the first and second source regions having the first conductivity type; forming a first body region having an opposite second conductivity type between the first and second trenches and between the first source region and the epitaxial layer, the first body region having a first depth below a top surface of the epitaxial layer, the first body region being formed by a first implantation process having a first implantation energy; and forming a second body region having the opposite second conductivity type between the second and third trenches and between the second source region and the epitaxial layer, the second body region having a greater second depth below the top surface, the second body region including a first portion and a second portion, the first portion being formed by the first implantation process having the first implantation energy and a second implantation process having a second implantation energy greater than the first implantation energy, and the second portion being formed by the second implantation process.

2 . The method of claim 1 , further comprising forming a first body contact electrically connected to the first body region and having a first width between the first and second trenches, and forming a second body contact electrically connected to the second body region and having a greater second width between the second and third trenches.

3 . The method of claim 1 , wherein the first, second and third polysilicon field plates have a top at a third depth below the top surface, the first depth being less than the third depth and the second depth being greater than the third depth.

4 . The method of claim 1 , further comprising forming third and fourth body regions located between the first and second trenches, the third body region extending the second depth between the top surface and the substrate and the fourth body region extending the first depth between the top surface and the substrate, the fourth body region located between the first and the third body regions.

5 . The method of claim 1 , further comprising forming a third body region located between the third trench and a fourth trench, the third body region extending the first depth between the top surface and the substrate.

6 . The method of claim 5 , wherein the first body region has a lateral width between the first and second trenches and the third body region has the lateral width between the third and fourth trenches, and the first and third body regions extend laterally parallel to the first, second, third and fourth trenches by a length that is at least two times the lateral width.

7 . A method of forming an integrated circuit, comprising:
forming first, second and third trenches in an epitaxial layer located over a semiconductor substrate, the epitaxial layer having a first conductivity type and a top surface; forming first, second and third field plates respectively within the first, second and third trenches; forming a first source region between the first and second trenches, and a second source region between the second and third trenches, the first and second source regions having the first conductivity type; forming a first body member within the epitaxial layer between the first and second trenches and between the first source region and the epitaxial layer, the first body member having a different second conductivity type and extending into the epitaxial layer a first distance between the top surface and the substrate, the first body member including a first portion and a second portion, the first portion being formed by a first implantation process having a first implantation energy and a second implantation process having a second implantation energy greater than the first implantation energy, and the second portion being formed by the second implantation process; and forming a second body member within the epitaxial layer between the second and third trenches and between the second source region and the epitaxial layer, the second body member having the different second conductivity type and extending into the epitaxial layer a lesser second distance between the top surface and the substrate, the second body member being formed by the first implantation process having the first implantation energy.

8 . The method of claim 7 , wherein the first, second and third field plates each have a top at a depth below the top surface, the first distance being greater than the depth and the second distance being less than the depth.

9 . The method of claim 7 , further comprising forming third and fourth body members located between the first and second trenches, the third body member extending the first distance between the top surface and the substrate and the fourth body member extending the second distance between the top surface and the substrate, the fourth body member located between the first and the third body members.

10 . The method of claim 7 , further comprising forming a third body member between the third trench and a fourth trench and a fourth body member located between the second and third trenches, the third body member extending the first distance between the top surface and the substrate, and the fourth body member extending the first distance between the top surface and the substrate, the fourth body member located directly between the first and the third body members.

11 . The method of claim 7 , further comprising forming a third body member located between the third trench and a fourth trench, the third body member extending the first distance between the top surface and the substrate.

12 . The method of claim 11 , wherein the first body member has a lateral width between the first and second trenches and the third body member has the lateral width between the third and fourth trenches, and the first and third body members extend laterally parallel to the first, second, third and fourth trenches by a length that is at least two times the lateral width.

13 . The method of claim 11 , further comprising forming a fourth body member located between the second and third trenches and extending the first distance between the top surface and the substrate, the second body member located directly between the first and third body members.

14 . A method of forming an integrated circuit, comprising:
forming trenches in an epitaxial layer having a first conductivity type over a substrate; forming a polysilicon field plate within a bottom portion of each of the trenches; forming a gate above the polysilicon field plate within each of the trenches; forming source regions having the first conductivity type between adjacent pairs of the trenches; forming body regions having an opposite second conductivity type extending from respective ones of the source regions to the epitaxial layer, a first subset of the body regions having a first depth below a top surface of the epitaxial layer, and a second subset of the body regions having a greater second depth below the top surface of the epitaxial layer and a bottom surface of the gate within each of the trenches.

15 . The method of claim 14 , further comprising forming a first body contact electrically conn

Assignees

• Texas Instruments Inc

Inventors

• Lee Meng-Chia
• Kim Sunglyong
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/0295

  using recessing of the source electrodes · CPC title