Determining a physically unclonable function (PUF) selection vector

Patent metadata

Field	Value
Publication number	US-12562925-B2
Application number	US-202418591554-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Mar 17, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Technologies for generating an M-bit selection vector for a selector circuit that receives as input M binary values from a set of entropy-generation elements and outputs N binary values responsive to the M-bit selection vector are described. N bits in the M-bit selection vector are set to a first logic state, and M-N bits of the M-bit selection vector are set to a second logic state. A determination of which N bits in the M-bit selection vector are set to the first logic state is determined by a process. The process includes determining an accumulated Hamming weight value for M bit positions of the M-bit selection vector using K samples and identifying N bit positions in the M-bit selection vector using the accumulated Hamming weight values. The process sets the N bits corresponding to the N bit positions in the M-bit selection vector to the first logic state.

First claim

What is claimed is:

1 . A device comprising:
a set of entropy-generation elements which, in response to a sample signal, provide at least M binary values; and a selector circuit coupled to the set of entropy-generation elements, the selector circuit to receive as input the M binary values from the set of entropy-generation elements and output N binary values, responsive to an M-bit selection vector, wherein M is larger than N, wherein N bits in the M-bit selection vector are set to a first logic state, wherein M-N bits of the M-bit selection vector are set to a second logic state, wherein a determination of which N bits in the M-bit selection vector are set to the first logic state is determined by: generating K samples from the set of entropy-generation elements, wherein each sample of the K samples has M-bits corresponding to M bit positions of the M-bit selection vector, and wherein the set of entropy-generation elements is reset between each sample being generated; determining an accumulated Hamming weight value for each of the M bit positions of the M-bit selection vector using the K samples; identifying, using the accumulated Hamming weight values, N bit positions in the M-bit selection vector; and setting the N bits corresponding to the N bit positions in the M-bit selection vector to the first logic state.

2 . The device of claim 1 , further comprising a hardware array having M bit positions corresponding to the M bit positions of the M-bit selection vector, wherein:
determining the accumulated Hamming weight value for each bit position of the M-bit selection vector comprises:
counting a number of times a bit value of the corresponding bit position is the first logic state; and
storing a count value equal to the number of times in the corresponding bit position of the hardware array; and
identifying the N bit positions in the M-bit selection vector comprises:
initializing an offset value, X, to zero;
iterating through the hardware array to identify all bit positions having the count value equal to zero plus X or K minus X, wherein the corresponding bit positions of the M-bit selection vector are set to the first logic state; and
incrementing the offset value and continuing the iterating through the hardware array responsive to a number of bit positions of the M-bit selection vector set to the first logic state being less than the N bits.

3 . The device of claim 1 , wherein the determination of which N bits in the M-bit selection vector are set to the first logic state is determined during an enrollment process of the device.

4 . The device of claim 1 , wherein the determination of which N bits in the M-bit selection vector are set to the first logic state is further determined by:
setting a first counter to K; sampling, using the first counter, M binary values from the set of entropy-generation elements K times to obtain the K samples; accumulating a total of M accumulated Hamming weight values for the K samples; after collecting the K samples, initializing a second counter to zero and an offset value to zero, wherein a value of the second counter represents a bit position in the M-bit selection vector; for each value of the second counter, assessing the respective accumulated Hamming weight value to determine if the accumulated Hamming weight value equals K minus the offset value or zero plus the offset value and setting the corresponding bit position to the first logic state; once all M accumulated Hamming weight values have been assessed, resetting the second counter and incrementing the offset value to obtain an incremented offset value; and whenever a bit position in the M-bit selection vector is set to the first logic state, assessing whether a number of bit positions of the M-bit selection vector set to the first logic state is equal to N, wherein the determination of which N bits in the M-bit selection vector are set to the first logic state continues until the number of bit positions of the M-bit selection vector set to the first logic state is equal to N.

5 . The device of claim 4 , further comprising a maximum-length linear-feedback shift register (LFSR) whose sequence size is the same as M, wherein, for each value of the second counter, a selection of which accumulated Hamming weight value to assess is determined by an output of the maximum-length LFSR.

6 . The device of claim 5 , wherein the maximum-length LFSR is seeded with a random value derived from one or more of the K samples from the set of entropy-generation elements.

7 . The device of claim 1 , further comprising processing logic coupled to the set of entropy-generation elements and the selector circuit, wherein the processing logic is to determine which N bits in the M-bit selection vector are set to the first logic state.

8 . A method comprising:
sampling a set of entropy-generation elements to generate K samples, wherein each sample of the K samples has M-bits corresponding to M bit positions of an M-bit selection vector, and wherein the set of entropy-generation elements is reset between each sample being generated; determining an accumulated Hamming weight value for each of the M bit positions of the M-bit selection vector using the K samples; identifying, using the accumulated Hamming weight values, N bit positions in the M-bit selection vector, wherein M is larger than N; setting N bits corresponding to the N bit positions in the M-bit selection vector to a first logic state, wherein M-N bits of the M-bit selection vector are set to a second logic state; and storing the M-bit selection vector as at least a portion of helper data associated with a device comprising the set of entropy-generation elements.

9 . The method of claim 8 , wherein setting the N bits in the M-bit selection vector is performed in an enrollment process, wherein, as part of a regeneration process, the method further comprises:
receiving as inputs M binary values from the set of entropy-generation elements; receiving the M-bit selection vector; and outputting N binary values, responsive to the M-bit selection vector.

10 . The method of claim 8 , wherein:
determining the accumulated Hamming weight value for each of the M bit positions of the M-bit selection vector comprises:
counting a number of times a bit value of a corresponding bit position in the K samples is the first logic state; and
storing a count value equal to the number of times in a corresponding bit position of a hardware array having M bit positions corresponding to M bit positions of the M-bit selection vector; and
identifying the N bit positions in the M-bit selection vector comprises:
initializing an offset value, X, to zero;
iterating through the hardware array to identify all bit positions having the count value equal to zero plus X or K minus X, wherein the corresponding bit positions of the M-bit selection vector are set to the first logic state; and
incrementing the offset value and continuing iterating through the hardware array responsive to a number of bit positions of the M-bit selection vector set to the first logic state being less than the N bits.

11 . The method of claim 8 , further comprising:
setting a first counter to K, wherein the first counter is used to sample M binary values from the set of entropy-generation elements K times to obtain the K samples; accumulating a total of M accumulated Hamming weight values for the K samples; after collecting the K samples, initializing a second counter to zero and an offset value to zero, wherein a value of the second counter represents a bit position in the M-bit selection vector; for each value of the second counter, assessing the respective

Assignees

• Cryptography Res Inc

Inventors

• Best Scott C

Classifications

• H04L9/0869

  involving random numbers or seeds · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title