Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location

Patent metadata

Field	Value
Publication number	US-9262256-B2
Application number	US-201314140243-A
Country	US
Kind code	B2
Filing date	Dec 24, 2013
Priority date	Dec 24, 2013
Publication date	Feb 16, 2016
Grant date	Feb 16, 2016

Abstract

Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

First claim

What is claimed is:

1. A processor comprising:
a processor core; and
a secure key manager component coupled to the processor core, wherein the secure key manager comprises:
a physically unclonable function (PUF) component; and
a dark-bit masking circuit, coupled to the PUF component, wherein the dark-bit masking circuit is to:
measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit, wherein the dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window;
output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit; and
set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.

2. The processor of claim 1 , wherein the PUF component comprises a cross-coupled inverter pair to output the PUF value.

3. The processor of claim 1 , wherein the dark-bit masking circuit comprises:
bit-transition logic to detect a transition in the PUF value during the dark-bit window and to output a dark signal in response to the detected transition; and
clock-gating logic to gate a clock signal to the PUF component in response to the dark signal.

4. The processor of claim 1 , wherein the dark-bit masking circuit comprises:
a master latch coupled to an output of the PUF component;
a slave latch coupled to the output of the master latch; and
an exclusive-OR (XOR) gate coupled to receive an output of the master latch and an output of the slave latch.

5. The processor of claim 4 , wherein the dark-bit masking circuit further comprises:
an AND gate coupled to receive an output of the XOR gate; and
a first NOR gate coupled to receive an output of the AND gate and the output of the slave latch.

6. The processor of claim 5 , wherein the dark-bit masking circuit further comprises:
a second NOR gate coupled to receive an output of the AND gate and a clock signal; and
a third NOR gate coupled to receive the output of the AND gate and the clock signal, wherein the PUF component comprises a cross-coupled inverter pair coupled to receive an output of the second NOR gate and an output of the third NOR gate.

7. The processor of claim 4 , wherein the dark-bit masking circuit further comprises:
a first NAND gate coupled to receive an output of the XOR gate; and
a second NAND gate coupled to receive an output of the first AND gate and the output of the slave latch.

8. The processor of claim 7 , wherein the dark-bit masking circuit further comprises:
a third NAND gate coupled to receive an output of the first AND gate and a clock signal; and
a fourth NAND gate coupled to receive the output of the first AND gate and the clock signal, wherein the PUF component comprises a cross-coupled inverter pair coupled to receive an output of the third NAND gate and an output of the fourth NAND gate.

9. A method comprising:
measuring, by dark-bit masking logic, a physically unclonable function (PUF) value of a PUF component of a processor multiple times during a dark-bit window;
detecting, by the dark-bit masking logic, whether the PUF value is a dark bit during the dark-bit window, wherein the dark bit indicates that the PUF value is unstable during the dark-bit window; and
setting, by the dark-bit masking logic, a PUF bit of the PUF component to be a specified value when the PUF value is the dark bit; and
outputting, by the dark-bit masking logic, the PUF value as the PUF bit when the PUF value is not the dark bit.

10. The method of claim 9 , wherein the measuring the PUF value comprises measuring, by the dark-bit masking logic, an output of a cross-coupled inverter pair.

11. The method of claim 9 , wherein the detecting whether the PUF value is the dark bit comprises:
detecting, by dark-bit masking logic, a transition in the PUF value during the dark-bit window; and
gating, by the dark-bit masking logic, a clock signal to the PUF component in response to the detecting the transition.

12. The method of claim 9 , wherein the detecting whether the PUF value is the dark bit comprises:
storing the PUF value in a master latch coupled to the PUF component, the master latch to output a first output;
storing an output of the master latch using a slave latch coupled to the master latch, the slave latch to output a second output; and
detecting a difference between the first output and the second output.

13. The method of claim 12 , further comprising resetting the dark-bit window by the dark-bit masking logic.

14. The method of claim 12 , wherein the dark-bit masking logic comprises logic circuitry.

15. The method of claim 12 , wherein the dark-bit masking logic is executed by a processing core of the processor.

16. An integrated circuit comprising:
a processor core;
a plurality of physically unclonable function (PUF) components to generate a hardware key, wherein each of the PUF components output a PUF bit of the hardware key; and
a dark-bit masking circuit coupled to the plurality of PUF components, wherein the dark-bit masking circuit is to determine unstable bits in the PUF bits of the hardware key and to set the unstable bits to be specified values.

17. The integrated circuit of claim 16 , wherein the PUF component comprises a cross-coupled inverter pair, and wherein the dark-bit masking circuit comprises:
bit-transition logic to detect a transition in the PUF value during a dark-bit window and to output a dark signal in response to the detected transition; and
clock-gating logic to gate a clock signal to the PUF component in response to the dark signal.

18. The integrated circuit of claim 16 , wherein the PUF component comprises a cross-coupled inverter pair, and wherein the dark-bit masking circuit comprises:
a master latch coupled to an output of the PUF component;
a slave latch coupled to the output of the master latch; and
an exclusive-OR (XOR) gate coupled to receive an output of the master latch and an output of the slave latch.

19. The integrated circuit of claim 18 , wherein the dark-bit masking circuit further comprises:
an AND gate coupled to receive an output of the XOR gate; and
a first NOR gate coupled to receive an output of the AND gate and the output of the slave latch.

20. The integrated circuit of claim 19 , wherein the dark-bit masking circuit further comprises:
a second NOR gate coupled to receive an output of the AND gate and a clock signal; and
a third NOR gate coupled to receive the output of the AND gate and the clock signal, wherein the PUF component comprises a cross-coupled inverter pair coupled to receive an output of the second NOR gate and an output of the third NOR gate.

21. The integrated circuit of claim 18 , wherein the dark-bit masking circuit further comprises:
a first NAND gate coupled to receive an output of the XOR gate; and
a second NAND gate coupled to receive an output of the first AND gate and the output of the slave latch.

22. The integrated circuit of claim 21 , wherein the dark-bit masking circuit further comprises:
a third NAND gate coupled to receive an output of the first AND gate and a clock signal; and
a fourth NAND gate coupled to receive the output of the first AND gate and the clock signal, wherein the PUF component comprises a cross-coupled inverter pair coupled to receive an output of the third NAND gate and an output of the fourth NAND gate.

Assignees

• Mathew Sanu K
• Satpathy Sudhir K
• Koeberl Patrick
• Li Jiangtao
• Krishnamurthy Ram K
• Rajan Anand
• Intel Corp

Inventors

• Mathew Sanu K
• Satpathy Sudhir K
• Koeberl Patrick
• Li Jiangtao
• Krishnamurthy Ram K
• Rajan Anand

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• G06F11/0745

  in an input/output transactions management context (input/output processing in general G06F13/00) · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• H04L9/34

  Bits, or blocks of bits, of the telegraphic message being interchanged in time {(for speech signals H04K1/06)} · CPC title