Magnetic coupling-based inter-chip wireless communication interface structure and method for three-dimensional stacked chips

Patent metadata

Field	Value
Publication number	US-12562772-B2
Application number	US-202318393698-A
Country	US
Kind code	B2
Filing date	Dec 22, 2023
Priority date	Dec 22, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Disclosed are a magnetic coupling-based inter-chip wireless communication interface structure and method for three-dimensional stacked chips. The interface structure includes a master chip and at least one slave chip, wherein the master chip and all the slave chips are vertically stacked; the slave chip includes a clock receiving module, a data transmitting module, and a data receiving module; the master chip includes a clock transmitting module, a data transmitting module, and a data receiving module. The solution herein makes use of the magnetic coupling relationship between on-chip spiral inductors of different chips in a vertical direction to simultaneously transmit data and clock signals. The communication method herein modulates each bit of digital signal into a differential bi-directional non-return-to-zero pulse train and performs decision and data parsing at the receiving end by a high-speed dynamic comparator.

First claim

What is claimed is:

1 . A magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips, comprising a master chip and at least one slave chip, wherein the master chip and the at least one slave chip are vertically stacked; the at least one slave chip comprises a clock receiving module, a data transmitting module and a data receiving module; the master chip comprises a clock transmitting module, a data transmitting module, and a data receiving module; on the at least one slave chip and the master chip, the data transmitting modules are identical, and the data receiving modules are identical; the data transmitting module on the at least one slave chip corresponds to the data receiving module on the master chip, and the data receiving module on the at least one slave chip corresponds to the data transmitting module on the master chip; the data transmitting module and the data receiving module that correspond to each other establish a magnetic coupling relationship in a vertical direction between a data transmitting inductor and a data receiving inductor that are parallelly aligned for transmission of a voltage signal;
the clock transmitting module comprises a clock transmitting inductor and a clock transmitting H-bridge; the clock receiving module comprises a clock receiving inductor, a differential amplifier and a clock output buffer chain; the clock transmitting module and the clock receiving module establish a magnetic coupling relationship in a vertical direction between the clock receiving inductor and the clock transmitting inductor that are parallelly aligned for transmission of a voltage signal; the clock transmitting inductor is connected to an output end of the clock transmitting H-bridge, and an external system clock is input to an input end of the clock transmitting H-bridge; the clock receiving inductor is connected to an input end of the differential amplifier, and a signal amplified by the differential amplifier is output to the clock output buffer chain; the data transmitting module comprises a rectangular wave pulse generator, a full-bit data modulator, and a data transmitting inductor, wherein the full-bit data modulator comprises an H-bridge controller and a full-bit H-bridge; the data receiving module comprises a data receiving inductor, a voltage-controlled clock delayer, a clocked dynamic comparator, and a latch; the data transmitting inductor is connected to an output end of the full-bit data modulator, and a pulse generated by the rectangular wave pulse generator and a data signal to be transmitted are input to the full-bit data modulator; an output of the clock receiving module is connected to the voltage-controlled clock delayer, and an output delay clock signal of the voltage-controlled clock delayer and a signal received by the data receiving inductor are together output to the clocked dynamic comparator; the clocked dynamic comparator is connected to the latch and outputs a recovered data signal.

2 . The magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips according to claim 1 , wherein the data transmitting inductor, the data receiving inductor, the clock transmitting inductor and the clock receiving inductor are made of a top metal of the chip, and the data transmitting inductor, the data receiving inductor, the clock transmitting inductor and the clock receiving inductor are rectangular or octagonal planar spiral inductors with a self-resonant frequency higher than a transmitting frequency.

3 . The magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips according to claim 1 , wherein the clock transmitting H-bridge comprises a symmetrical pair of inverters; both ends of the clock transmitting inductor are respectively connected to output ends of the pair of inverters of the clock transmitting H-bridge; the pair of inverters is driven by a pair of differential rectangular wave system clocks.

4 . The magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips according to claim 1 , wherein the full-bit H-bridge is composed of two pairs of fully symmetric PMOS and NMOS with drains connected, wherein a source of the PMOS is connected to a power supply and a source of the NMOS is connected to ground; the H-bridge controller is connected to four gate input ends of the PMOS and NMOS on left and right arms of the full-bit H-bridge; a complementary signal to the data signal to be transmitted is input into a PMOS gate on the left arm; the data signal to be transmitted is directly connected to the PMOS gate on the right arm; the data signal to be transmitted and a rectangular wave pulse generated by the rectangular wave pulse generator are output to a NMOS gate on the left arm via a NOR gate; an opposite signal of the data signal to be transmitted and an opposite signal of the generated rectangular wave pulse are output to the NMOS gate on the right arm via the NOR gate.

5 . The magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips according to claim 1 , wherein the voltage-controlled clock delayer is a delay circuit where voltage controls delay time or phase without changing a signal frequency and a duty cycle.

6 . The magnetic coupling-based inter-chip wireless communication interface structure for three-dimensional stacked chips according to claim 1 , wherein the clocked dynamic comparator is a high-speed comparator for implementing a pre-charging state and comparing differential inputs of a state flow in a working cycle controlled by high and low levels of a clock; a polarity and magnitude of an output differential level of the clocked dynamic comparator are positively related to the magnitude and magnitude of an amplitude difference of an input differential signal in a comparison state.

7 . A magnetic coupling-based inter-chip wireless communication method for three-dimensional stacked chips applied to the interface structure according to claim 1 , comprising:
step 1), inputting an external system clock signal to the clock transmitting H-bridge of the master chip, sensing a periodic voltage signal with a same frequency as a system clock of the master chip by the clock receiving inductor of the at least one slave chip, and amplifying the periodic voltage signal by differential amplifier of the at least one slave chip to recover the rectangular wave system clock; and step 2), sending the data signal from the data transmitting module of the master chip to the data receiving module of the at least one slave chip, or sending from the data transmitting module of the at least one slave chip to the data receiving module of the master chip, wherein the master chip or at least one slave chip for transmitting data is referred to as a transmitting chip, the at least one slave chip or master chip for receiving data is referred to as a receiving chip, and a process of sending the data signal comprises: 2.1), using a transmitting chip clock to generate, by the data transmitting module of the transmitting chip, a rectangular pulse wave with a same frequency as the transmitting chip clock and a duty ratio of less than 50%; 2.2), passing the rectangular pulse wave generated by the transmitting chip in step 2.1) in a direction from a positive end to a negative end all through the data transmitting inductor therein by the data transmitting module of the transmitting chip in a time slot where the data to be transmitted is of a high level; likewise, in the time slot where the data to be transmitted is of a zero level, passing the rectangular pulse wave generated by the transmitting chip in step 2.1) a

Assignees

• Univ Zhejiang
• Jcet Group Co Ltd

Inventors

• Zhu Xiaolei
• Sun Chonghui
• Yang Kun
• Tao Rushuo
• Yang Cheng

Classifications

• H03F3/2173

  of the bridge type · CPC title

• H03K5/249

  using clock signals · CPC title

• H03F3/45273

  Mirror types · CPC title

• H04B1/40 Primary

  Circuits · CPC title

• H04L12/02 Primary

  Details · CPC title