Clock generator and voltage generation circuit including the same

Patent metadata

Field	Value
Publication number	US-12562726-B2
Application number	US-202318490579-A
Country	US
Kind code	B2
Filing date	Oct 19, 2023
Priority date	Jun 15, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A clock generator includes a voltage supply circuit configured to generate a control voltage based on a first current and a control signal. The clock generator also includes a first clock output circuit configured to output the control signal by comparing a first reference voltage with the control voltage, and to output a first clock signal by comparing a third reference voltage having a different voltage level from the first reference voltage with the control voltage. clock generator further includes a second clock output circuit configured to compare a second reference voltage with the control voltage, to compare a fourth reference voltage having a different voltage level from the second reference voltage with the control voltage, and to generate a second clock signal having a phase different from that of the first clock signal.

First claim

What is claimed is:

1 . A clock generator comprising:
a voltage supply circuit configured to generate a control voltage based on a first current and a control signal; a first clock output circuit configured to output the control signal by comparing a first reference voltage with the control voltage, and to output a first clock signal by comparing a third reference voltage having a different voltage level from the first reference voltage with the control voltage; and a second clock output circuit configured to compare a second reference voltage with the control voltage, to compare a fourth reference voltage having a different voltage level from the second reference voltage with the control voltage, and to generate a second clock signal having a phase different from that of the first clock signal.

2 . The clock generator according to claim 1 , wherein:
the second reference voltage is set to have a lower level than the first reference voltage, the third reference voltage is set to have a lower level than the second reference voltage, and the fourth reference voltage is set to have a lower level than the third reference voltage.

3 . The clock generator according to claim 1 , further comprising a current generator configured to generate the first current, wherein the current generator includes:
a reference current source configured to generate a reference current; and a current mirror circuit configured to generate the first current by mirroring the reference current.

4 . The clock generator according to claim 3 , wherein the current mirror circuit includes:
a first transistor connected between a power voltage terminal and the reference current source, the first transistor configured to have a gate terminal and a drain terminal that are commonly connected to each other; and a second transistor connected between the power voltage terminal and the reference current source, the second transistor configured to have a gate terminal that is commonly connected to the gate terminal of the first transistor.

5 . The clock generator according to claim 4 , wherein:
the reference current source is connected between the first transistor and a ground voltage terminal.

6 . The clock generator according to claim 1 , wherein the voltage supply circuit includes:
a first switching element connected between an input terminal of the first current and an output terminal of the control voltage, the first switching element controlled by the control signal of the control signal; a second switching element connected between an output terminal of the control voltage and a ground voltage terminal, the second switching element controlled by an inversion signal; and a first capacitor connected between the output terminal of the control voltage and the ground voltage terminal.

7 . The clock generator according to claim 6 , wherein the voltage supply circuit is configured such that:
when the first switching element is turned on by deactivation of the control signal, the first capacitor is charged according to the first current so that a level of the control voltage increases; and the second switching element is turned on by activation of the control signal so that the control voltage is discharged.

8 . The clock generator according to claim 1 , wherein the first clock output circuit includes:
a first comparator configured to output a first comparison signal by comparing the control voltage with the first reference voltage; a second comparator configured to output a second comparison signal by comparing the control voltage with the third reference voltage; a first latch circuit configured to output the control signal by latching the first comparison signal and the second comparison signal; and a combination circuit configured to output the first clock signal by logically combining the control signal with the second comparison signal.

9 . The clock generator according to claim 8 , wherein the second clock output circuit includes:
a third comparator configured to output a third comparison signal by comparing the control voltage with the second reference voltage; a fourth comparator configured to output a fourth comparison signal by comparing the control voltage with the fourth reference voltage; a switching controller configured to generate a switching control signal based on the third comparison signal and the fourth comparison signal; a drive controller configured to generate a driving signal based on the third comparison signal and the fourth comparison signal, and to selectively control a filtering signal corresponding to the driving signal based on the switching control signal; a driver configured to control the filtering signal based on the third comparison signal, the fourth comparison signal, and an output signal of the drive controller; a pull-down driver configured to pull-down drive an output terminal of the filtering signal in response to an inversion signal of the switching control signal; and a delay circuit configured to output the second clock signal by delaying the filtering signal.

10 . The clock generator according to claim 9 , wherein the drive controller includes:
a logic combination element configured to generate the driving signal by logically combining the third comparison signal with the fourth comparison signal; and a third switching element configured to selectively output the driving signal as the filtering signal based on the switching control signal.

11 . The clock generator according to claim 9 , wherein the second clock output circuit is configured such that:
during a period in which the control voltage is lower than the fourth reference voltage and the first comparison signal is activated, when the third switching signal is turned off by deactivation of the switching control signal, a connection terminal between the driving signal and the filtering signal is cut off; and when the pull-down driver is turned on by activation of an inversion signal of the switching control signal, the filtering signal is pull-down driven.

12 . The clock generator according to claim 9 , wherein the driver includes:
a third transistor and a fourth transistor connected in series between a power voltage terminal and an output terminal of the filtering signal; and a fifth transistor and a sixth transistor connected in series between an output terminal of the filtering signal and a ground voltage terminal, wherein
each of the third transistor and the fifth transistor is configured to receive the third comparison signal through a gate terminal thereof;
the fourth transistor is configured to receive an inversion signal of the fourth comparison signal through a gate terminal thereof; and
the sixth transistor is configured to receive the fourth comparison signal through a gate terminal thereof.

13 . The clock generator according to claim 9 , wherein the switching controller includes:
a voltage transfer circuit configured to selectively supply a power voltage and a ground voltage based on a transfer control signal; a second latch circuit configured to latch an output signal of the voltage transfer circuit; a switching control signal output circuit configured to output the switching control signal based on an output signal of the second latch circuit; and a control signal generator configured to generate the transfer control signal by logically combining the third comparison signal with the fourth comparison signal.

14 . The clock generator according to claim 1 , wherein the second clock output circuit includes:
a third comparator configured to output a third comparison signal by c

Assignees

• Sk Hynix Inc

Inventors

• Lee Junghan

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H04N25/7795

  Circuitry for generating timing or clock signals · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03K3/53

  by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback (H03K3/335 takes precedence) · CPC title