Phase error correction for clock signals

Patent metadata

Field	Value
Publication number	US-10833665-B2
Application number	US-201916551263-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Dec 11, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.

First claim

What is claimed is:

1. A multi-phase clock generator circuit comprising:
a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal;
a phase error correction circuit configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal, the error signal being applied to the phase reference signal to correct for phase errors in the multi-phase clock signal and produce a corrected phase reference signal; and
a comparator configured to compare a ramp signal and the corrected phase reference signal to produce the multi-phase clock signal.

2. The multi-phase clock generator circuit of claim 1 , further comprising a synchronization ramp generator circuit arranged to generate the ramp signal in synchronization with the synchronization clock signal.

3. The multi-phase clock generator circuit of claim 2 , further comprising:
a sample and hold circuit configured to sample the ramp signal in response to a sample signal and to provide the peak ramp signal; and
a buffer circuit coupled to receive the sampled peak ramp signal, the buffer circuit having an output terminal coupled to provide a buffered peak ramp signal to the phase error correction circuit.

4. The multi-phase clock generator circuit of claim 3 , wherein the phase reference generator circuit comprises:
a resistor network coupled between the output terminal of the buffer circuit and electrical ground; and
a switch tap network configured to tap a respective intermediate node of the resistor network based on the phase selection signal.

5. The multi-phase clock generator circuit of claim 4 , wherein the switch tap network comprises switch devices coupled between respective intermediate nodes of the resistor network and an output of the phase reference generator circuit, one of the switch devices being activated to tap a respective intermediate node in response to the phase selection signal.

6. The multi-phase clock generator circuit of claim 4 , wherein the resistor network comprises a set of resistors connected in series between the output terminal of the buffer circuit and electrical ground.

7. The multi-phase clock generator circuit of claim 1 , wherein the phase error correction circuit further comprises a transconductance amplifier configured to generate the error signal as an error current signal having an amplitude based on a phase error signal and a reference voltage, wherein the phase error signal is representative of an error between the multi-phase clock signal and the synchronization clock signal.

8. The multi-phase clock generator circuit of claim 7 , wherein the phase reference generator circuit comprises:
a buffer circuit configured to receive the peak ramp signal and to provide a buffered peak ramp signal;
a resistor network coupled between an output terminal of the buffer circuit and electrical ground; and
a switch tap network configured to tap a respective intermediate node of the resistor network based on the phase selection signal and provide a corresponding tapped resistance at a node corresponding to an input of the comparator receiving the phase reference signal, wherein the phase error correction circuit is further configured to provide the error current signal directly to the node such that the phase reference signal is compensated to provide the corrected phase reference signal.

9. The multi-phase clock generator circuit of claim 8 , wherein the phase error correction circuit further comprises:
an error capacitor coupled to an input of the amplifier receiving the phase error signal;
a charge current source configured to provide a charging current to charge the error capacitor during a charge period of each clock cycle;
a discharge current source configured to provide a discharging current to discharge the error capacitor during a discharge period of each clock cycle;
wherein the phase error signal is supplied to the amplifier based on the charging and discharging of the error capacitor.

10. The multi-phase clock generator circuit of claim 9 , wherein each of the charge current source and the discharge current source is configured to set a respective current magnitude based on the phase selection signal.

11. The multi-phase clock generator circuit of claim 9 , wherein the transconductance amplifier is configured to have a gain that is constant over frequency and the discharge current source is configured such that the discharging current is set proportional to frequency of the multi-phase clock signal.

12. The multi-phase clock generator circuit of claim 9 , wherein the transconductance amplifier is configured to have a gain that is fixed and the transconductance amplifier is configured such that Id*T*(1−Npi/Np)/Vsync_pk is set to a constant value, where
Id is the discharging current,
T is the period of the multi-phase clock signal,
Vsync_pk is the buffered peak ramp signal,
Npi is a selected phase of the multi-phase clock signal, and
Np is a number of phases.

13. The multi-phase clock generator circuit of claim 9 , wherein the transconductance amplifier is configured such that Gme*(1−Npi/Np) is set to a first constant value, and Id*T/Vsync_pk is set to a second constant value, where
Gme is the transconductance of the transconductance amplifier,
Id is the discharging current,
T is the period of the multi-phase clock signal,
Vsync_pk is the buffered peak ramp signal,
Npi is a selected phase of the multi-phase clock signal, and
Np is a number of phases.

14. The multi-phase clock generator circuit of claim 9 , wherein the multi-phase clock generator circuit is configured to satisfy the following equation:
R 0* Gme*Id/Ce*T/V sync_ pk *(1− Npi/Np )≈1

where:
R 0 is a total resistance of resistors in the resistor network,
Gme is a gain of the transconductance amplifier,
Id is the discharging current,
Ce is the capacitance of the error capacitor,
T is the period of the multi-phase clock signal,
Vsync_pk is a voltage of the buffered peak ramp signal,
Npi is a selected phase of the multi-phase clock signal, and
Np is a number of phases.

15. The multi-phase clock generator circuit of claim 1 , further comprising synchronization timing logic configured to control timing of the ramp signal based on the synchronization clock signal.

16. The multi-phase clock generator circuit of claim 1 , further comprising a synchronization clock generator that is configured to generate the synchronization clock signal internally within the multi-phase clock generator circuit or externally from the multi-phase clock generator circuit.

17. A multi-phase clock generator circuit comprising:
a ramp generator that includes an output;
a comparator having first and second inputs and a clock output, the first input being coupled to the output of the ramp generator;
a peak detector circuit having an input coupled to the output of the ramp generator;
a buffer having an input coupled to an output of the peak detector circuit;
a phase reference generator circuit having an input coupled to an output of the buffer and having an output coupled to the second input of the comparator; and
a phase error correction circuit having an input coupled to the clock output and having an output coupled to the second input of the comparator.

18. The circuit of claim 17 , wherein
the peak detector circuit is configured to provide a peak ramp signal at the output of the peak detector circuit based on a ramp signal provided at the output of the ramp gene

Assignees

• Texas Instruments Inc

Inventors

• Jiang Jianfeng

Classifications

• H02M3/1586

  switched with a phase shift, i.e. interleaved · CPC title

• H02M3/1582

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H03K5/1515

  non-overlapping · CPC title

• H03K5/15066

  using bistable devices (H03K5/15093 takes precedence) · CPC title

• H03K5/22 Primary

  Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00) · CPC title