Programmable delays and methods thereof

Patent metadata

Field	Value
Publication number	US-12562723-B2
Application number	US-202217648788-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Jan 24, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.

First claim

The invention claimed is:

1 . A programmable edge delay circuit comprising:
an input node configured to receive an input signal; an output node configured to provide as an output signal a delayed version of the input signal; a first inverter circuit connected to the input node, wherein the first inverter circuit comprises a first state-programmable field-effect transistor that is programmable to a first remanent polarization state or a second remanent polarization state different from the first remanent polarization state; and a second inverter circuit connected between the first inverter circuit and the output node, wherein the second inverter circuit comprises a second state-programmable field-effect transistor that is programmable to the first remanent polarization state or the second remanent polarization state, wherein the first state-programmable field-effect transistor is in the first remanent polarization state and the second state-programmable field-effect transistor is in the second remanent polarization state, wherein a longer timing delay is provided on one edge of the input signal while providing a shorter delay on the other edge of the input signal.

2 . The programmable delay circuit of claim 1 , wherein the first and second inverter circuits comprise: a p-type spontaneously polarizable field-effect transistor connected with an n-type field-effect transistor, wherein the p-type spontaneously polarizable field-effect transistor comprises the first or the second state-programmable memory element; a p-type field-effect transistor connected with an n-type spontaneously polarizable field-effect transistor, wherein the n-type spontaneously polarizable field-effect transistor comprises the first or the second state-programmable memory element; or a p-type spontaneously polarizable field-effect transistor connected with an n-type spontaneously polarizable field-effect transistor, wherein the p-type spontaneously polarizable field-effect transistor comprises the first state-programmable memory element and the n-type spontaneously polarizable field-effect transistor comprises the second state-programmable memory element.

3 . The programmable delay circuit of claim 1 , further comprising a first level-limiting circuit connected at an intermediate input node between the input node and the first and second inverter circuits, and a second level-limiting circuit connected at an intermediate output node between one inverter circuit of the first and second inverter circuits and the output node.

4 . The programmable delay circuit of claim 3 , wherein the first level-limiting circuit is configured to decouple an input voltage level at the input node from a programming voltage level at the intermediate input node; and/or wherein the second level-limiting circuit is configured to decouple an output voltage level at the output node from a programming voltage level at the intermediate output node.

5 . The programmable delay circuit of claim 1 , further comprising an additional pair of inverter circuits coupled in series between the first and second inverter circuits and the output node, wherein the additional pair of inverter circuits is configurable to provide an additional adjustable delay for the signal transmitted from the input node to the output node.

6 . The programmable edge delay circuit of claim 1 , wherein the first state-programmable field-effect transistor and the second state-programmable field-effect transistor each comprise a ferroelectric field-effect transistor.

7 . The programmable edge delay circuit of claim 1 , wherein the first remanent polarization state is a high voltage threshold state, and the second remanent polarization state is a low voltage threshold state.

8 . A method for operating a programmable delay circuit according to claim 1 , the method comprising:
receiving a programming signal at the input node to program the first and second inverter circuits; and receiving an input signal at the input node of the programmable edge delay circuit; and providing the input signal with a delay to an output node.

Assignees

• Ferroelectric Memory Gmbh

Inventors

• Sivero Stefano

Classifications

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C8/00

  Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03K2005/00195

  using FET's · CPC title