Gate drive circuit and method for driving same, and display device

Patent metadata

Field	Value
Publication number	US-12562094-B2
Application number	US-202318701296-A
Country	US
Kind code	B2
Filing date	Jul 31, 2023
Priority date	Aug 31, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Provided is a gate drive circuit, including a plurality of shift registers and buffers in cascade, wherein each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal.

First claim

The invention claimed is:

1 . A gate drive circuit, comprising a plurality of shift registers and buffers in cascade, wherein
each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal, and rising edge time of the second gate scanning signal is less than rising edge time of the first gate scanning signal; wherein the shift register comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first storage capacitor, and a second storage capacitor; and wherein a control electrode of the first transistor is connected to a first clock signal terminal, a first electrode of the first transistor is connected to a first signal input terminal, and a second electrode of the first transistor is connected to a first node; the first node is a junction of the second electrode of the first transistor, a first electrode of the second transistor, a control electrode of the fourth transistor, and a first electrode of the eighth transistor; a control electrode of the second transistor is connected to a second clock signal terminal, the first electrode of the second transistor is connected to the first node, and a second electrode of the second transistor is connected to a first electrode of the third transistor; a control electrode of the third transistor is connected to a second node, the first electrode of the third transistor is connected to a first level signal terminal, and a second electrode of the third transistor is connected to the second electrode of the second transistor; the second node is a junction of the control electrode of the third transistor, a second electrode of the fourth transistor, a second electrode of the fifth transistor, a control electrode of the sixth transistor, and a first electrode plate of the first storage capacitor; the control electrode of the fourth transistor is connected to the first node, a first electrode of the fourth transistor is connected to the first clock signal terminal, and the second electrode of the fourth transistor is connected to the second node; a control electrode of the fifth transistor is connected to the first clock signal terminal, a first electrode of the fifth transistor is connected to a second level signal terminal, and the second electrode of the fifth transistor is connected to the second node; the control electrode of the sixth transistor is connected to the second node, a first electrode of the sixth transistor is connected to the first level signal terminal and a second electrode plate of the first storage capacitor, and a second electrode of the sixth transistor is connected to a first gate scanning signal output terminal; a control electrode of the seventh transistor is connected to a third node, a first electrode of the seventh transistor is connected to the second clock signal terminal, and a second electrode of the seventh transistor is connected to the first gate scanning signal output terminal and a second electrode plate of the second storage capacitor; the third node is a junction of the control electrode of the seventh transistor, a second electrode of the eighth transistor, and a first electrode plate of the second storage capacitor; a control electrode of the eighth transistor is connected to the second level signal terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is connected to the third node; the first electrode plate of the first storage capacitor is connected to the second node, and the second electrode plate of the first storage capacitor is connected to the first level signal terminal and the first electrode of the sixth transistor; and the first electrode plate of the second storage capacitor is connected to the third node, and the second electrode plate of the second storage capacitor is connected to the first gate scanning signal output terminal and the second electrode of the seventh transistor.

2 . The gate drive circuit according to claim 1 , wherein the buffer comprises an even quantity of inverters in cascade; and wherein each of the inverters is configured to perform waveform inversion on the first gate scanning signal once.

3 . The gate drive circuit according to claim 2 , wherein the buffer comprises a first inverter and a second inverter, the first inverter comprises a ninth transistor and a tenth transistor, the second inverter comprises an eleventh transistor and a twelfth transistor, the ninth transistor and the tenth transistor have opposite polarities, and the eleventh transistor and the twelfth transistor have opposite polarities; and wherein
a control electrode of the ninth transistor is connected to the first gate scanning signal output terminal of the shift register, a first electrode of the ninth transistor is connected to a first power supply voltage terminal, and a second electrode of the ninth transistor is connected to a control electrode of the eleventh transistor and a control electrode of the twelfth transistor; a control electrode of the tenth transistor is connected to the first gate scanning signal output terminal of the shift register, a first electrode of the tenth transistor is connected to a second power supply voltage terminal, and a second electrode of the tenth transistor is connected to the control electrode of the eleventh transistor and the control electrode of the twelfth transistor; the control electrode of the eleventh transistor is connected to the second electrode of the ninth transistor and the second electrode of the tenth transistor, a first electrode of the eleventh transistor is connected to the first power supply voltage terminal, and a second electrode of the eleventh transistor is connected to a second gate scanning signal output terminal; and the control electrode of the twelfth transistor is connected to the second electrode of the ninth transistor and the second electrode of the tenth transistor, a first electrode of the twelfth transistor is connected to the second power supply voltage terminal, and a second electrode of the twelfth transistor is connected to the second gate scanning signal output terminal.

4 . The gate drive circuit according to claim 3 , further comprising a level shifter; and wherein
the level shifter is configured to provide a first level signal and a second level signal to the shift register according to a preset timing, wherein the first level signal and the second level signal have opposite polarities.

5 . The gate drive circuit according to claim 4 , wherein the level shifter comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; and wherein
a control electrode of the thirteenth transistor is connected to a second signal input terminal, a first electrode of the thirteenth transistor is connected to the first power supply voltage terminal, and a second electrode of the thirteenth transistor is connected to a control electrode of the fifteenth transistor and a second electrode of the sixteenth transistor; a control electrode of the fourteenth transistor is connected to the second signal input terminal, a first electrode of the fourteenth transistor is connected to the first power supply voltage terminal, and a second electrode of the fourteenth

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Jiang Shanghong
• Li Dachao
• Fan Longfei
• Ma Yaoxi
• Lu Pengcheng
• Yang Shengji
• Chen Xiaochuan

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title