Scan driving circuit

Patent metadata

Field	Value
Publication number	US-2017005642-A1
Application number	US-201514783100-A
Country	US
Kind code	A1
Filing date	Aug 10, 2015
Priority date	Jul 2, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

A scan driving circuit configured for driving cascaded scan lines is provided, which includes an input control module, a latch module, a driving-signal generation module, an output control module, a constant high voltage source and a constant low voltage source. The scan driving circuit of the present invention drives the input control module through cascade signals of a preceding stage and cascade signals of a succeeding stage, so as to reduce interference and the driving power consumption of the scan driving circuit.

First claim

What is claimed is:

1 . A scan driving circuit configured for driving cascaded scan lines, the scan driving circuit comprising:
an input control module inputted with a first clock signal of a current stage, cascade signals of a preceding stage, and cascades signal of a succeeding stage, and for generating a control signal based upon the first clock signal of the current stage, the cascade signals of the preceding stage, and the cascade signals of the succeeding stage; a latch module for performing a latch operation for the control signal; a driving-signal generation module for generating a driving signal based upon the control signal and a second clock signal of the current stage; an output control module for outputting a scanning signal of the current stage based upon the driving signal; a constant high voltage source for providing a high voltage; and a constant low voltage source for providing a low voltage, wherein an inverted signal of the control signal is used as cascade signals on the current stage and outputted into the scan driving circuit on the succeeding stage, wherein the input control module includes a 19th switching transistor, a 20th switching transistor, a 21st switching transistor, a 22nd switching transistor, a 23rd switching transistor, and a 24th switching transistor, wherein a control end of the 19th switching transistor is connected with an output end of the driving-signal generation module, an input end of the 19th switching transistor is connected with the constant high voltage source, and an output end of the 19th switching transistor is connected with a control end of the 21st switching transistor and a control end of the 22nd switching transistor, wherein a control end of the 20th switching transistor is connected with the output end of the driving-signal generation module, an input end of the 20th switching transistor is connected with the constant low voltage source, and an output end of the 20th switching transistor is connected with the control end of the 21st switching transistor and the control end of the 22nd switching transistor, wherein an input end of the 21st switching transistor is connected with the constant high voltage source, and an output end of the 21st switching transistor is connected with a control end of the 23rd switching transistor and a control end of the 24th switching transistor, wherein an input end of the 22nd switching transistor is connected with the constant low voltage source, and an output end of the 22nd switching transistor is connected with the control end of the 23rd switching transistor and the control end of the 24th switching transistor, wherein an input end of the 23rd switching transistor is connected with the constant high voltage source, and an output end of the 23rd switching transistor is connected with an output end of the output control module, wherein an input end of the 24th switching transistor is connected with the constant low voltage source, and an output end of the 24th switching transistor is connected with the output end of the input control module, wherein the 19th switching transistor, the 21st switching transistor and the 23rd switching transistor are PMOS transistors, and the 20th switching transistor, the 22nd switching transistor and the 24th switching transistor are NMOS transistors.

2 . The scan driving circuit as claimed in claim 1 , wherein the input control module includes a 1st switching transistor, a 2nd switching transistor, a 3rd switching transistor, a 4th switching transistor, a 5th switching transistor and a 6th switching transistor,
wherein a control end of the 1st switching transistor is inputted with the first clock signal of the current stage, an input end of the 1st switching transistor is connected with the constant high voltage source, and an output end of the 1st switching transistor is connected with an output end of the input control module, wherein a control end of the 2nd switching transistor is inputted with the cascade signals of the preceding stage, an input end of the 2nd switching transistor is connected with the constant high voltage source, and an output end of the 2nd switching transistor is connected with an input end of the 3rd switching transistor, wherein a control end of the 3rd switching transistor is inputted with the cascade signals on the succeeding stage, and an output end of the 3rd switching transistor is connected with the output end of the input control module, wherein a control end of the 4th switching transistor is inputted with the first clock signal of the current stage, an input end of the 4th switching transistor is connected with an output end of the 5th switching transistor, and an output end of the 4th switching transistor is connected with the output end of the input control module, wherein a control end of the 5th switching transistor is inputted with the cascade signals of the preceding stage, and an input end of the 5th switching transistor is connected with the constant low voltage source, wherein a control end of the 6th switching transistor is inputted with the cascade signals of the succeeding stage, an input end of the 6th switching transistor is connected with the constant low voltage source, and an output end of the 6th switching transistor is connected with the output end of the 5th switching transistor.

3 . The scan driving circuit as claimed in claim 2 , wherein the 1st switching transistor, the 2nd switching transistor and the 3rd switching transistor are PMOS transistors, and the 4th switching transistor, the 5th switching transistor and the 6th switching transistor are NMOS transistors.

4 . The scan driving circuit as claimed in claim 1 , wherein the input control module includes a 1st switching transistor, a 2nd switching transistor, a 3rd switching transistor, a 4th switching transistor, a 5th switching transistor and a 6th switching transistor,
wherein a control end of the 1st switching transistor is inputted with the first clock signal of the current stage, an input end of the 1st switching transistor is connected with the constant high voltage source, and an output end of the 1st switching transistor is connected with an output end of the input control module, wherein a control end of the 2nd switching transistor is inputted with the cascade signals of the preceding stage, an input end of the 2nd switching transistor is connected with the constant high voltage source, and an output end of the 2nd switching transistor is connected with an input end of the 3rd switching transistor, wherein a control end of the 3rd switching transistor is inputted with the cascade signals of the succeeding stage, and an output end of the 3rd switching transistor is connected with the output end of the input control module, wherein a control end of the 4th switching transistor is inputted with the first clock signal of the current stage, an input end of the 4th switching transistor is connected with the constant low voltage source, and an output end of the 4th switching transistor is connected with an input end of the 5th switching transistor, wherein a control end of the 5th switching transistor is inputted with the cascade signals of the preceding stage, and an output end of the 5th switching transistor is connected with the output end of the input control module, wherein a control end of the 6th switching transistor is inputted with the cascade signals of the succeeding stage, an input end of the 6th switching transistor is connected with the input end of the 5th switching transistor, and an output end of the 6th switching transistor is connected with the output end of the input control module.

5 . The scan driving circuit as claimed in claim 4 , wherein the 1st switching transistor, the 2nd switching transistor and the 3rd switching tran

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Zhao Mang
• Tian Yong
• Chen Gui
• Chen Caiqin
• Zhang Xin

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title