SPUF based on combinational logic and scan chain

Patent metadata

Field	Value
Publication number	US-12561504-B2
Application number	US-202218087829-A
Country	US
Kind code	B2
Filing date	Dec 23, 2022
Priority date	Mar 30, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An SPUF based on combinational logic and scan chain comprises an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW 0 , SW 1 , . . . , SWn− 1 , n=2m, and m is an integer greater than or equal to 1; combinational logic circuit module comprises n switch circuits S 0 , S 1 , . . . , Sn− 1 and a combinational logic circuit; the scan chain circuit module comprises n scan flip-flops (SFFs) SFF 0 , SFF 1 , . . . , SFFn− 1 ; each of the n switch circuits SW 0 , SW 1 , . . . , SWn− 1 and the n switch circuits S 0 , S 1 , . . . , Sn− 1 is implemented by a 2-to-1 multiplexer. The SPUF based on combinational logic and scan chain has high uniqueness and randomness, requires a few clock frequency changes, and has high reliability, more bits of responses and high security.

First claim

What is claimed is:

1 . An SPUF based on combinational logic and scan chain, comprising: an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW 0 , SW 1 , . . . , SW n-1 , n=2 m , and m is an integer greater than or equal to 1; the external stimulus source has n first data output terminals, n stimulus output terminals, n second data output terminals, n selective control output terminals, a first control terminal, a second control terminal and a clock output terminal; the combinational logic circuit module has n first data input terminals, n second data input terminals, n control input terminals, n data output terminals, and n combinational logic paths, and a maximum path delay of the n combinational logic paths is denoted as T path ; the scan chain circuit module has a scan data input terminal, a test control input terminal, a clock input terminal, n data input terminals, n data output terminals, and a deviation data output terminal; the n switch circuits SW 0 , SW 1 , . . . , SW n-1 each have a first data input terminal, a second data input terminal, a control input terminal and a data output terminal; the data processing module has a data input terminal and a response output terminal; the n first data output terminals of the external stimulus source are connected to the n first data input terminals of the combinational logic circuit module in a one-to-one correspondence manner, the n stimulus output terminals of the external stimulus source are connected to the n control input terminals of the combinational logic circuit module in a one-to-one correspondence manner, the first control terminal of the external stimulus source is connected to the scan data input terminal of the scan chain circuit module, the second control terminal of the external stimulus source is connected to the test control input terminal of the scan chain circuit module, the clock output terminal of the external stimulus source is connected to the clock input terminal of the scan chain circuit module, the n second data output terminals of the external stimulus source are connected to the first data input terminals of the n switch circuits SW 0 , SW 1 , . . . , SW n-1 in a one-to-one correspondence manner, the n selective control output terminals of the external stimulus source are connected to the control input terminals of the n switch circuits SW 0 , SW 1 , . . . , SW n-1 in a one-to-one correspondence manner, the n th data output terminal of the combinational logic circuit module is connected to the second data input terminal of the switch circuit SW 0 , the first to the (n−1) th data output terminals of the combinational logic circuit module are connected to the second data input terminals of the switch circuits SW 1 , . . . , SW n-1 in a one-to-one correspondence manner, the data output terminals of the n switch circuits SW 0 , SW 1 , . . . , SW n-1 are connected to the n data input terminals of the scan chain circuit module in a one-to-one correspondence manner, the n data output terminals of the scan chain circuit module are connected to the n second data input terminals of the combinational logic circuit module in a one-to-one correspondence manner, the deviation data output terminal of the scan chain circuit module is connected to the data input terminal of the data processing module, and the response output terminal of the data processing module is configured to output PUF response data;
the n first data output terminals of the external stimulus source are used for outputting n path stimulus signals which each has n-bit, the k th n-bit path stimulus signal is used for activating the k th combinational logic path in the combinational logic circuit module, and k=0, 1, 2, . . . , n−1; the n stimulus output terminals of the external stimulus source are used for outputting n combinational logic circuit input control signal which each has n-bit; the n selective control output terminals of the external stimulus source are used for outputting selective control signals; the n switch circuits SW 0 , SW 1 , . . . , SW n-1 turn on first data input terminals or second data input terminals of the n switch circuits SW 0 , SW 1 , . . . , SW n-1 according to selective control signals input to control input terminals of the n switch circuits SW 0 , SW 1 , . . . , SW n-1 ; data output by the data output terminal of the j th switch circuit SW j is input to the j th data input terminal of the scan chain circuit module, and is configured to control the j th data output terminal of the scan chain circuit module to produce a signal transition, so as to generate and output a scan flip-flop stimulus signal, wherein j=0, 1, 2, . . . , n−1; the clock output terminal of the external stimulus source is configured to output five clock signals to the clock input terminal of the scan chain circuit module, and the five clock signals are an initialization clock signal comprising n clock cycles with a time period, a reference clock signal comprising 2n clock cycles with the time period, an over-clock signal comprising 2n clock cycles with a time period ranging from 70% to 100% of the time period, an output clock signal comprising n(n+1)/2 clock cycles with the time period, and a deviation output clock signal comprising n(n+1)/2 clock cycles with the time period, wherein the time period=T path ; the first control terminal of the external stimulus source is configured to output a first control signal, which is configured to control initialization of the n data output terminals of the scan chain circuit module; the second control terminal of the external stimulus source is configured to output a second control signal, which is a high level signal or a low level signal and is configured to control the n data output terminals of the scan chain circuit module to output a high level signal or a low level signal; when the second control signal is a high level signal, the n data output terminals of the scan chain circuit module output a high level signal; when the second control signal is a low level signal, the n data output terminals of the scan chain circuit module output a low level signal;
the combinational logic circuit module comprises n switch circuits S 0 , S 1 , . . . , Sn− 1 and a combinational logic circuit, wherein the n switch circuits S 0 , S 1 , . . . , S n-1 each have a first data input terminal, a second data input terminal, a control input terminal and a data output terminal, the combinational logic circuit has the n combinational logic paths with the maximum path delay T path , each combinational logic path has an input terminal and an output terminal, the input terminals of the n combinational logic paths are correspondingly n input terminals of the combinational logic circuit, the output terminals of the n combinational logic paths are correspondingly n output terminals of the combinational logic circuit, the input terminal of the j th combinational logic path is the j th input terminal of the combinational logic circuit, the output terminal of the j th combinational logic path is the j th output terminal of the combinational logic circuit, the n output terminals of the combinational logic circuit are taken as the n data output terminals of the combinational logic circuit module, the data output terminals the n switch circuits S 0 , S 1 , . . . , S n-1 are connected to the n input terminals of the combinational logic circuit in a one-to-one correspondence manner, the first data input terminals of the n switch circuits S 0 , S 1 , . . . , S n-1 are taken as the n second data input terminals of the combinational logic circuit module, the second data input terminals of the n switch circuits S 0 , S 1 , . . . , S n-1 are taken as the n first data input terminals of the combinational logic circuit module, and the control input terminals of the n switch circuits S

Assignees

• Univ Wenzhou

Inventors

• Wang Pengjun
• Chen Jia
• Zhang Yue Jun
• Li Gang
• Zhuang Youyi

Classifications

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F21/71 Primary

  to assure secure computing or processing of information · CPC title