Logic and flip-flop circuit timing margins controlled based on scan-pattern transition processing

Patent metadata

Field	Value
Publication number	US-11146252-B2
Application number	US-202016799053-A
Country	US
Kind code	B2
Filing date	Feb 24, 2020
Priority date	Feb 24, 2020
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.

First claim

What is claimed is:

1. In an integrated circuit having application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits, a method carried out by the integrated circuit and comprising:
controlling timing-based logic states of the flip-flop circuits based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and
setting respective logic states of the flip-flop circuits in instances where due to degradations, actual setup and hold times do not satisfy criteria for the specified minimum setup and hold times.

2. The method of claim 1 , further including assessing whether to set respective ones of the flip-flop circuits to an opposing one of two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

3. The method of claim 1 , further including assessing whether historically respective ones of the flip-flop circuits are likely to have been set predominantly in one of the two logic states and, in response, setting said respective ones of the flip-flop circuits to another one of the two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

4. The method of claim 1 , wherein the application logic circuitry operates at an application clock frequency, and further including operating the application logic circuitry while using a clock frequency slightly above the application clock frequency, and in response assessing whether to set respective ones of the flip-flop circuits to the opposing one of two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

5. The method of claim 1 , wherein the application logic circuitry operates at an application clock frequency, and further including testing the application logic circuitry while using a clock frequency slightly above the application clock frequency to determine that respective ones of the flip-flop circuits are susceptible to failures relating to setup and/or hold time margins, and in response, setting the respective ones of the flip-flop circuits in appropriate logic states, as constant logic states, during times when the flip-flop circuits are inactive.

6. The method of claim 1 , wherein the integrated circuit includes scan-pattern test circuitry to operate the application logic circuitry, when the flip-flop circuits are inactive, at a clock frequency slightly above a clock frequency normally used by the application logic circuitry, and further including using the scan-pattern test circuitry at different occurrences post-manufacture to assess whether to set respective ones of the flip-flop circuits to the opposing one of two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

7. The method of claim 1 , wherein the integrated circuit includes scan-pattern test circuitry to operate the application logic circuitry, and further including, at different times in post-manufacture use, automatically detecting that the application logic circuitry is inactive and in response operating the application logic circuitry by using a clock frequency slightly above a clock frequency normally used by the application logic circuitry and by causing the application logic circuitry to process a scan-pattern to assess whether to set respective ones of the flip-flop circuits to certain constant logic states.

8. The method of claim 1 , wherein the application logic circuitry operates at an application clock frequency, and further including testing the application logic circuitry while using a clock frequency slightly above the application clock frequency and using timing estimates of data and clock paths from the testing to alter operability of one of the flip-flop circuits by causing advancement of a data edge, relative to a clock edge, of said one of the flip-flop circuits.

9. The method of claim 1 , wherein the application logic circuitry operates at an application clock frequency, and further including testing the application logic circuitry while using a clock frequency slightly above the application clock frequency and using timing estimates of data and clock paths from the testing to alter operability of one of the flip-flop circuits by causing delay of an input data edge, relative to a clock edge, of said one of the flip-flop circuits.

10. The method of claim 1 , wherein the degradations have been influenced at least in part due to bias temperature instability.

11. An apparatus comprising:
application logic circuitry including flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits; and
control circuitry to control timing-based logic states of the flip-flop circuits based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry, and to set logic states of the flip-flop circuits in instances where due to degradations, actual setup and hold times do not satisfy criteria for the specified minimum setup and hold times.

12. The apparatus of claim 11 , wherein the control logic is to assess whether to set respective ones of the flip-flop circuits to an opposing one of two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

13. The apparatus of claim 11 , wherein the control circuitry is to assess whether historically respective ones of the flip-flop circuits are likely to have been set predominantly in one of the two logic states and, in response, to set said respective ones of the flip-flop circuits to another one of the two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

14. The apparatus of claim 11 , wherein the application logic circuitry is to operate at an application clock frequency, and wherein the control circuitry is to test the application logic circuitry while using a clock frequency slightly above the application clock frequency, and in response to assess whether to set respective ones of the flip-flop circuits to the opposing one of two logic states, as a constant logic state, during times when the flip-flop circuits are inactive.

15. The apparatus of claim 11 , wherein the application logic circuitry is to operate at an application clock frequency, and wherein the control circuitry is to operate the application logic circuitry while using a clock frequency slightly above the application clock frequency to determine that respective ones of the flip-flop circuits are susceptible to failures relating to setup/hold time margins, and in response, setting the respective ones of the flip-flop circuits in appropriate logic states, as constant logic states, during times when the flip-flop circuits are inactive.

16. The apparatus of claim 11 , wherein the integrated circuit includes scan-pattern test circuitry to test the application logic circuitry, when the flip-flop circuits are inactive, at a clock frequency slightly above a clock frequency normally used by the application logic circuitry, and wherein using the scan-pattern test circuitry is to provide, at different occurrences post-manufacture, at least one test vector to the application logic to assess whether the control circuitry is to set respective ones of the flip-flop circuits to the opposing one of two logic states, as a constant logic state, during times when t

Assignees

• Nxp Bv

Inventors

• Schat Jan-Peter

Classifications

• G01R31/2882

  Testing timing characteristics · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title