Encoding and decoding variable length instructions

Patent metadata

Field	Value
Publication number	US-12561139-B2
Application number	US-202418406527-A
Country	US
Kind code	B2
Filing date	Jan 8, 2024
Priority date	Nov 23, 2016
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.

First claim

What is claimed is:

1 . Decoding hardware comprising:
hardware logic configured to determine an encoding type from a fetched instruction word; word selection logic configured to generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either the fetched instruction word or a predicted instruction word, and to concatenate the instruction words in the ordered sequence to form an encoded instruction; re-order hardware logic configured to re-order bits in the encoded instruction to generate a decoded instruction; and an output arranged to output the decoded instruction.

2 . The decoding hardware according to claim 1 , wherein the word selection logic is further configured to remove one or more control bits from the fetched instruction words prior to generating the ordered sequence of instruction words.

3 . The decoding hardware according to claim 1 , wherein the word selection logic is further configured to remove any control bits from the fetched instruction words prior to generating the ordered sequence of instruction words.

4 . The decoding hardware according to claim 1 , wherein the fetched instruction word comprises one or more control bits and wherein the word selection logic is configured to perform the selection of the fetched instruction word or a corresponding predicted instruction word based on values of one or more of the control bits.

5 . The decoding hardware according to claim 1 , wherein the fetched instruction word is selected from an ordered sequence of fetched instruction words and the word selection logic is configured to generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a next corresponding fetched instruction word or a corresponding predicted instruction word.

6 . The decoding hardware according to claim 5 , wherein the word selection logic is configured to perform the selection of either a next fetched instruction word in the ordered sequence of fetched instruction words or a corresponding predicted instruction word based upon a value of a bit in a mask identified based on an encoding type.

7 . The decoding hardware according to claim 1 , wherein the re-order hardware logic is configured to re-order bits in the encoded instruction according to the encoding type to generate a decoded instruction by re-ordering bits in the encoded instruction based on mapping data identified based on an encoding type.

8 . The decoding hardware according to claim 1 , wherein the hardware logic is configured to determine an encoding type, wherein the hardware logic is further arranged to determine the encoding type from one or more control bits in the fetched instruction word.

9 . The decoding hardware according to claim 8 , wherein the encoding type corresponds to a type of Arithmetic Logic Unit (ALU) on which the instruction will be executed.

10 . A method of decoding instructions comprising:
determining an encoding type from a fetched instruction word; generating an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, the fetched instruction word or a predicted instruction word; concatenating the instruction words in the ordered sequence to form an encoded instruction and re-ordering bits in the encoded to generate a decoded instruction; and outputting the decoded instruction.

11 . The method according to claim 10 , further comprising:
fetching, in a fetch stage of a processor, an instruction word from memory.

12 . The method according to claim 11 , wherein the fetched instruction word is selected from one of a pre-defined number of instruction words.

13 . An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes decoding hardware as set forth in claim 1 ; a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the decoding hardware; and an integrated circuit generation system configured to manufacture the decoding hardware according to the circuit layout description.

14 . A method comprising:
receiving, at an input, mapping data for an instruction set and instruction data describing instructions in an instruction set in canonical form; parsing the mapping data and instruction data using a grammar library; generating, in a code and data generation engine, both encoding software and a hardware description of a decoder based on the parsed mapping data and instruction data, wherein the decoder comprises decoding hardware as set forth in claim 1 ; and outputting the encoding software and the hardware description of a decoder.

15 . The method according to claim 14 , further comprising:
generating debugging data and documentation in human-readable form in the code and data generation engine and based on the parsed mapping data and instruction data; and outputting the debugging data and documentation in human-readable form.

Assignees

• Imagination Tech Ltd

Inventors

• Nield Simon Thomas
• Mccarthy James

Classifications

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/3856

  Reordering of instructions, e.g. using queues or age tags · CPC title

• G06F9/30152

  Determining start or end of instruction; determining instruction length · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F8/443

  Optimisation · CPC title