Integrated circuit chip including back side power delivery tracks

Patent metadata

Field	Value
Publication number	US-12557634-B2
Application number	US-202217932582-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Sep 16, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices at its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

First claim

What is claimed is:

1 . An integrated circuit (IC) chip comprising:
a semiconductor substrate having a front surface and a back surface; active devices at the front surface of the semiconductor substrate, isolated from each other by an isolation dielectric layer; mutually parallel power rails extending in one direction and buried in the semiconductor substrate and/or in the isolation dielectric layer; through semiconductor via connections (TSVs), connecting the power rails to the back surface of the semiconductor substrate; and power delivery tracks on the back surface of the semiconductor substrate, oriented transversely with respect to the power rails and connected to the power rails by the TSVs, wherein:
the power delivery tracks are part of a power delivery network configured to be coupled to a supply voltage and to a reference voltage,
the power delivery tracks are configured to be alternately connected to the supply voltage and to the reference voltage,
the TSVs are arranged so that the power rails are equally configured to be alternately connected to the supply voltage and the reference voltage,
the TSVs are formed as elongate slit-shaped volumes aligned to the power rails, and
the TSVs are arranged in a staggered pattern, so that when any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and another power delivery track directly adjacent to the one power delivery track is connected to a second row of mutually parallel TSVs which are staggered relative to the TSVs of the first row, the second row being directly adjacent the first row.

2 . The IC chip according to claim 1 , wherein the TSVs of the staggered pattern have essentially a same length (L TSV ), and wherein a distance (S TSV ) between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is essentially the same across the staggered pattern.

3 . The IC chip according to claim 2 , wherein the distance (S TSV ) between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is smaller than or equal to the length (L TSV ) of the TSVs.

4 . The IC chip according to claim 3 , wherein the distance (S TSV ) between two directly adjacent TSVs which are mutually aligned along their longitudinal direction is essentially equal to the length (L TSV ) of the TSVs, and wherein all the power delivery tracks have essentially a same width (W BM ) and are configured by an essentially constant distance (S BM ) between directly adjacent power delivery tracks.

5 . The IC chip according to claim 4 , wherein the width (W BM ) of the power delivery tracks is essentially equal to the distance (S BM ) between directly adjacent power delivery tracks.

6 . The IC chip according to claim 1 , wherein the power rails are at least partially buried in the isolation dielectric layer and not in the substrate.

7 . The IC chip according to claim 1 , wherein the active devices are fin-based devices or nano-sheet based devices and wherein the power rails run parallel to the fins or to the nano-sheets.

8 . The IC chip according to claim 1 , wherein the power delivery tracks are essentially perpendicular to the buried power rails.

9 . A method of producing an integrated circuit (IC) chip according to claim 1 , the method comprising:
providing a device wafer comprising a semiconductor substrate on an upper surface; producing slits in the semiconductor substrate, according to the staggered pattern, the slits going through the complete thickness of the semiconductor substrate; filling the slits with an electrically conductive material; etching back the conductive material in the slits from the front surface of the semiconductor substrate to a certain depth thereby producing the staggered TSVs from a remaining conductive material in the slits and depositing a dielectric material on each top of the TSVs; producing active devices including contacts at the front surface of the semiconductor substrate, the active devices being isolated from each other by an isolation dielectric layer, the active devices defining at least part of a front end of line portion of the IC chip; by etching trenches from the front side of the device wafer to tops of the TSVs, each trench being etched into a dielectric material disposed on a top of a corresponding TSV, and by filling the trenches with an electrically conductive material, producing the power rails aligned to the TSVs, so that any two directly adjacent power rails are connected, respectively, to two groups of mutually staggered TSVs; producing electrical conductors on the front side of the device wafer, the electrical conductors connecting the power rails to a plurality of the contacts, producing a back end of line portion of the IC chip on the front end of line portion; flipping the wafer with created TSVs and power rails and bonding it to a carrier wafer; thinning the device wafer until the TSVs are exposed on the back surface of the semiconductor substrate; and producing the power delivery tracks transversely with respect to the TSVs.

10 . The method according to claim 9 , wherein the device wafer comprises a base wafer, an etch stop layer on the base wafer, and the semiconductor substrate on the etch stop layer, and wherein the etch stop function of the etch stop layer is related to stopping an etch process applied during the thinning of the device wafer.

11 . The method according to claim 9 , wherein the power delivery tracks are essentially perpendicular to the power rails.

Assignees

• Imec Vzw

Inventors

• Beyne Eric
• Jourdain Anne
• Veloso Anabela

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title