Forming a planar semiconductor surface

Patent metadata

Field	Value
Publication number	US-12557571-B2
Application number	US-202318340201-A
Country	US
Kind code	B2
Filing date	Jun 23, 2023
Priority date	Jun 23, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method for producing a planar semiconductor surface includes forming a workpiece that has a carrier substrate, one or more insulating layers, a semiconductor layer, a first etch stop layer, and a second etch stop layer; forming a contact on the workpiece; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer.

First claim

What is claimed is:

1 . A method for producing a planar semiconductor surface, the method comprising:
forming a workpiece that has a carrier substrate, one or more insulating layers on the carrier substrate, a semiconductor layer on the one or more insulating layers, a first etch stop layer on the semiconductor layer, and a second etch stop layer on the first etch stop layer; forming a contact on the workpiece; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact, wherein the first voltage is different than the second voltage; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer, wherein the first etch stop layer has a first doping type, and the second etch stop layer has a second doping type that is different than the first doping type.

2 . The method according to claim 1 , wherein the workpiece has a third etch stop layer on the second etch stop layer, the method further comprising:
biasing the workpiece to a third voltage through the contact, wherein the third voltage is different than the second voltage; and etching the third etch stop layer and part of the second etch stop layer with the photo-electrochemical etching and the third voltage that selectively removes the third etch stop layer faster than the second etch stop layer.

3 . The method according to claim 1 , wherein the semiconductor layer is an intrinsic layer.

4 . The method according to claim 3 , further comprising:
forming the semiconductor layer on the first etch stop layer.

5 . The method according to claim 1 , wherein:
the first etch stop layer has a first doping concentration; and the second etch stop layer has a second doping concentration, wherein the second doping concentration is lower than the first doping concentration.

6 . The method according to claim 5 , wherein the first doping concentration and the second doping concentration are in a range of approximately 1×10 18 dopants per cubic centimeters to approximately 1×10 17 dopants per cubic centimeters.

7 . The method according to claim 1 , wherein:
the first etch stop layer has a first thickness; and the second etch stop layer has a second thickness, wherein the second thickness is greater than the first thickness.

8 . The method according to claim 7 , wherein the first thickness and the second thickness are in a range of approximately 10 nanometers to approximately 10 micrometers.

9 . The method according to claim 1 , further comprising:
measuring an etch current through the contact during the photo-electrochemical etching.

10 . The method according to claim 9 , further comprising:
setting a bias voltage used in the photo-electrochemical etching to less than 0.2 volts from a peak voltage at which a peak etch current is measured through the contact.

11 . The method according to claim 9 , wherein the second etch stop layer is an n-type silicon carbide, the first etch stop layer is a p-type silicon carbide, and the second voltage used in the photo-electrochemical etching is higher than a peak voltage that creates a peak etch current for the p-type silicon carbide such that the p-type silicon carbide is passivated and stops etching.

12 . The method according to claim 9 , wherein the etch current drops in response to etching through the second etch stop layer.

13 . The method according to claim 1 , wherein the planar surface on the semiconductor layer varies by no greater than 10 nanometers over a 100 millimeter diameter wafer.

14 . The method according to claim 1 , further comprising:
forming the workpiece on a sacrificial substrate.

15 . The method according to claim 14 , further comprising:
removing the sacrificial substrate before the forming of the contact.

16 . A semiconductor device with a planar surface fabricated in accordance with claim 1 .

17 . A method for producing a planar semiconductor surface, the method comprising:
forming a workpiece that has a carrier substrate, a semiconductor layer, a first etch stop layer on the semiconductor layer, a second etch stop layer on the first etch stop layer, and a sacrificial substrate on the second etch stop layer; removing the sacrificial substrate; forming a contact on the workpiece after the sacrificial substrate has been removed; biasing the workpiece to a second voltage through the contact; etching the second etch stop layer and part of the first etch stop layer with a photo-electrochemical etching and the second voltage that selectively removes the second etch stop layer faster than the first etch stop layer; biasing the workpiece to a first voltage through the contact, wherein the first voltage is different than the second voltage; and etching the first etch stop layer and part of the semiconductor layer with the photo-electrochemical etching and the first voltage that selectively removes the first etch stop layer faster than the semiconductor layer to produce a semiconductor device with a planar surface on the semiconductor layer.

18 . The method according to claim 17 , further comprising:
forming the semiconductor layer on the first etch stop layer.

19 . The method according to claim 17 , further comprising:
forming the first etch stop layer with a first doping type; and forming the second etch stop layer with a second doping type, wherein the first doping type is different than the second doping type.

20 . The method according to claim 1 , wherein:
the first etch stop layer is doped with a p-type dopant, and the second etch stop layer is doped with an n-type dopant.

Assignees

• Boeing Co

Inventors

• Cui Shanying
• Whiteley Samuel J
• Graetz Jason A
• Vajo John J
• Sorensen Adam E

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title