Phase change memory with reduced programming current

US12557565B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12557565-B2
Application numberUS-202217653309-A
CountryUS
Kind codeB2
Filing dateMar 3, 2022
Priority dateMar 3, 2022
Publication dateFeb 17, 2026
Grant dateFeb 17, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of manufacturing a phase change memory (PCM) device, the method comprising: forming a heater on a substrate; forming a hardmask to cover a top surface of the heater; forming a phase change material layer on and contacting a first lateral side of the heater; forming a first electrode on the phase change material layer on the first lateral side of the heater; and forming a second electrode on the substrate on a second lateral side of the heater, the second electrode contacting both the heater and the hardmask, wherein the PCM device is configured such that contact between the first lateral side of the heater and a lower lateral side portion of the phase change material layer enables formation of an amorphous portion of the phase change material layer having a half mushroom shape when performing a RESET operation with resistive heating. 2 . The method according to claim 1 , wherein the heater has a stripe shape and is formed along a central portion of the substrate. 3 . The method according to claim 1 , wherein a height of the amorphous portion of the phase change material layer is greater than a height of the heater. 4 . The method according to claim 1 , wherein the heater comprises at least one selected from the group consisting of titanium nitride (TiN), silicon carbide (SiC), graphite, tantalum nitride (TaN), tungsten nitride (WN), titanium tungsten (TiW), and titanium aluminide (TiAl). 5 . The method according to claim 1 , wherein the hardmask comprises at least one selected from the group consisting of SiN, a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), and a boron nitride (BN). 6 . The method according to claim 1 , wherein the phase change material layer includes at least one selected from the group consisting of GeSe, AsS, SbTe and In 2 Se 3 GeAsTe, or GeSbTe (GST). 7 . The method according to claim 1 , wherein the phase change material layer is doped with at least one selected from the group consisting of aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), (tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), cerium oxide (CeO 2 ), silicon nitride (SiN), and silicon oxynitride (SiON). 8 . The method according to claim 1 , wherein a thickness of the first electrode is less than a thickness of the second electrode. 9 . The method according to claim 1 , wherein the phase change material layer comprises GST. 10 . A semiconductor device comprising: a heater on a substrate; a hardmask covering a top surface of the heater; a phase change material layer on and contacting a first lateral side of the heater; a first electrode on the phase change material layer on the first lateral side of the heater; and a second electrode on the substrate on a second lateral side of the heater, the second electrode contacting both the heater and the hardmask, wherein the PCM device is configured such that contact between the first lateral side of the heater and a lower lateral side portion of the phase change material layer enables formation of an amorphous portion of the phase change material layer having a half mushroom shape when performing a RESET operation with resistive heating. 11 . The semiconductor device according to claim 10 , wherein the heater has a stripe shape and is formed along a central portion of the substrate. 12 . The semiconductor device according to claim 10 , wherein a height of the amorphous portion of the phase change material layer is greater than a height of the heater. 13 . The semiconductor device according to claim 10 , wherein the heater comprises at least one selected from the group consisting of titanium nitride (TiN), silicon carbide (SiC), graphite, tantalum nitride (TaN), tungsten nitride (WN), titanium tungsten (TiW), and titanium aluminide (TiAl). 14 . The semiconductor device according to claim 10 , wherein the hardmask comprises at least one selected from the group consisting of SiN, a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), and a boron nitride (BN). 15 . The semiconductor device according to claim 10 , wherein the phase change material layer includes at least one selected from the group consisting of GeSe, AsS, SbTe and In 2 Se 3 GeAsTe, or GeSbTe (GST). 16 . The semiconductor device according to claim 10 , wherein the phase change material layer is doped with at least one selected from the group consisting of aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), (tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), cerium oxide (CeO 2 ), silicon nitride (SiN), and silicon oxynitride (SiON). 17 . The semiconductor device according to claim 10 , wherein a thickness of the first electrode is less than a thickness of the second electrode. 18 . The semiconductor device according to claim 10 , wherein the phase change material layer comprises GST.

Assignees

Inventors

Classifications

  • Tellurides, e.g. GeSbTe · CPC title

  • H10N70/231Primary

    based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

  • Modification of switching materials after formation, e.g. doping (shaping H10N70/061) · CPC title

  • Formation of switching materials, e.g. deposition of layers · CPC title

  • Selenides, e.g. GeSe · CPC title

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Frequently asked questions

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What does patent US12557565B2 cover?
A semiconductor device is provided. The semiconductor device includes a heater formed on a substrate; a hardmask formed on the heater; a phase change material layer formed on a first side of the heater and the hardmask; a first electrode formed on the phase change material layer on the first side; and a second electrode formed on the substrate on a second side of the heater and the hardmask.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10N70/231. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 17 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).