Self-aligned backside contact with protruding source/drain

Patent metadata

Field	Value
Publication number	US-12557359-B2
Application number	US-202318329668-A
Country	US
Kind code	B2
Filing date	Jun 6, 2023
Priority date	Jun 6, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a PFET source/drain (S/D). The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate, and an NFET S/D. The NFET S/D may include a silicon (Si)-based epi protruding into the BILD plane and a SiGe epi between the BILD and the Si-based.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a PFET source/drain (S/D) comprising:
a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate;
an NFET S/D comprising:
a silicon (Si)-based epi protruding into the BILD plane; and
a SiGe epi between the BILD and the Si-based epi, wherein the NFET S/D comprises a first critical dimension (CD) between the first gate and a second gate, and a second CD below the BILD plane, wherein the first CD is smaller than the second CD.

2 . The semiconductor structure of claim 1 , further comprising a backside PFET contact electrically connecting the PFET S/D to a backside power delivery network.

3 . The semiconductor structure of claim 1 , further comprising a backside NFET contact electrically connecting the NFET S/D to a backside power delivery network through the SiGe epi.

4 . The semiconductor structure of claim 1 , further comprising a gate between the NFET S/D and a second NFET S/D, wherein the gate comprises a high-K metal gate (HKMG) that contacts the BILD.

5 . The semiconductor structure of claim 1 , wherein the PFET S/D comprises a third CD between the first gate and a third gate, and a fourth CD below the BILD plane, wherein the first CD is smaller than the second CD.

6 . The semiconductor structure of claim 1 , wherein the SiGe epi wraps around the Si-based epi and fully insulates the NFET S/D from the BILD.

7 . A method, comprising:
forming nanosheet fins above a substrate at a first critical dimension (CD); forming a first recess in the substrate between a first pair of the nanosheet fins, wherein the first recess comprises a second CD below the nanosheet fins; forming a silicon germanium (SiGe) liner within the recess; forming a NFET epi within the SiGe epi; and removing traces of the SiGe epi from channel layers of the nanosheet fins.

8 . The method of claim 7 , further comprising:
forming a second recess in the substrate between a second pair of the nanosheet fins, wherein the second recess comprises the second CD; and forming a PFET epi within the second recess.

9 . The method of claim 8 , further comprising forming a backside S/D contact electrically connected to the PFET epi.

10 . The method of claim 7 , wherein forming the first recess in the substrate between the first pair of the nanosheet fins comprises:
forming a protective liner on the nanosheet fins; etching the first recess vertically into the substrate in a first step; and etching the first recess laterally in a second step after the first step.

11 . The method of claim 7 , further comprising forming a backside S/D contact electrically connected to the NFET epi.

12 . The method of claim 7 , further comprising replacing the substrate with a backside interlayer dielectric (BILD).

13 . A semiconductor structure, comprising:
an NFET source/drain (S/D) comprising:
a silicon (Si)-based epi protruding into a BILD plane between a backside interlayer dielectric (BILD) and a first gate; and
a SiGe epi between the BILD and the Si-based epi; and
a backside NFET contact electrically connecting the NFET S/D to a backside power delivery network, wherein the NFET S/D comprises a first critical dimension (CD) between the first gate and a second gate, and a second CD below the BILD plane, wherein the first CD is smaller than the second CD, and wherein the second CD comprises a width of the SiGe epi.

14 . The semiconductor structure of claim 13 , further comprising a gate between the NFET S/D and a second NFET S/D, wherein the gate comprises a high-k metal gate (HKMG) that contacts the BILD.

15 . The semiconductor structure of claim 13 , wherein the SiGe epi wraps around the Si-based epi and fully insulates the NFET S/D from the BILD.

16 . The semiconductor structure of claim 13 , further comprising a PFET S/D comprising a SiGe-based epi protruding into the BILD plane and a backside PFET contact electrically connecting the PFET S/D to the backside power delivery network.

17 . The semiconductor structure of claim 16 , further comprising a gate between the PFET S/D and a second PFET S/D, wherein the gate comprises a high-K metal gate (HKMG) that contacts the BILD.

Assignees

• IBM

Inventors

• Xie Ruilong
• Choi Kisik
• Park Chanro
• Mochizuki Shogo
• Yamashita Tenko

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title