Semiconductor device including gate with different laterally adjacent sections and method

Patent metadata

Field	Value
Publication number	US-12557330-B2
Application number	US-202318127041-A
Country	US
Kind code	B2
Filing date	Mar 28, 2023
Priority date	Mar 28, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.

First claim

What is claimed is:

1 . A device comprising:
a semiconductor layer; a gate including:
a first gate section including: a first gate dielectric layer on the semiconductor layer; and a first gate conductor layer on the first gate dielectric layer; and
a second gate section including: a second gate dielectric layer on the semiconductor layer and further extending onto the first gate conductor layer; and a second gate conductor layer on the second gate dielectric layer, wherein the second gate dielectric layer is thinner than the first gate dielectric layer;
a gate sidewall spacer on the first gate conductor layer of the first gate section and positioned laterally adjacent to the second gate dielectric layer and the second gate conductor layer of the second gate section; and an isolation structure positioned laterally immediately adjacent to the first gate dielectric layer and the first gate conductor layer of the first gate section opposite a lower portion of the second gate section, wherein the isolation structure extends into the semiconductor layer.

2 . The device of claim 1 , further comprising:
a first well region within the semiconductor layer; and a second well region within the semiconductor layer positioned laterally adjacent to the first well region and having a different type conductivity than the first well region, wherein the first gate section is adjacent to the first well region and the second gate section is adjacent to the second well region.

3 . The device of claim 2 ,
wherein the first well region and the second well region are separated by an additional region of the semiconductor layer having a same type conductivity as the second well region at a lower conductivity level, and wherein at least the first gate section is adjacent to at least a portion of the additional region.

4 . The device of claim 2 , further comprising: a drain region immediately adjacent to the first well region and electrically isolated from the first gate section;
and a source region immediately adjacent to the second well region and electrically isolated from the second gate section.

5 . The device of claim 4 , wherein the isolation structure is further positioned laterally between the first gate section and the drain region and extends into the first well region within the semiconductor layer.

6 . The device of claim 1 , wherein the first gate dielectric layer includes an insulator layer, and wherein the first gate conductor layer includes a monocrystalline semiconductor layer.

7 . The device of claim 1 , wherein the second gate dielectric layer includes a high-K gate dielectric layer, and wherein the second gate conductor layer includes a metallic gate conductor layer.

8 . The device of claim 1 , wherein the second gate conductor layer includes a polycrystalline semiconductor layer.

9 . The device of claim 1 , further comprising metal silicide layers on the first gate section and the second gate section.

10 . The device of claim 1 , further comprising a shared gate contact extending to the first gate section and the second gate section, wherein the shared gate contact is offset from an active device region.

11 . The device of claim 1 , further comprising: a first gate contact extending to the first gate section; and a second gate contact extending to the second gate section, wherein the first gate contact and the second gate contact are offset from an active device region.

12 . The device of claim 11 , wherein the first gate contact and the second gate contact are electrically connected to a same gate bias voltage source.

13 . The device of claim 11 , wherein the first gate contact and the second gate contact are electrically connected to different gate bias voltage sources.

14 . A device comprising:
a semiconductor layer; a gate including:
a first gate section including: a first gate dielectric layer on the semiconductor layer; a first gate conductor layer on the first gate dielectric layer; and an additional gate conductor layer on the first gate conductor layer; and
a second gate section including: a second gate dielectric layer on the semiconductor layer and further extending onto the first gate conductor layer, and a second gate conductor layer on the second gate dielectric layer, wherein the second gate dielectric layer is thinner than the first gate dielectric layer;
a gate sidewall spacer on the first gate conductor layer of the first gate section and positioned laterally between the second gate dielectric layer and the second gate conductor layer of the second gate section and the additional gate conductor layer of the first gate section; and an isolation structure positioned laterally immediately adjacent to the first gate dielectric layer and the first gate conductor layer of the first gate section opposite a lower portion of the second gate section, wherein the isolation structure extends into the semiconductor layer.

15 . The device of claim 14 , further comprising:
a first well region within the semiconductor layer; and a second well region within the semiconductor layer positioned laterally adjacent to the first well region and having a different type conductivity than the first well region, wherein the first gate section is adjacent to the first well region and the second gate section is adjacent to the second well region.

16 . The device of claim 15 ,
wherein the first well region and the second well region are separated by an area of the semiconductor layer having a same type conductivity as the second well region at a lower conductivity level, and wherein at least the first gate section is adjacent to at least a portion of the area.

17 . The device of claim 15 , further comprising: a drain region adjacent to the first well region and electrically isolated from the first gate section; and a source region adjacent to the second well region and electrically isolated from the second gate section.

18 . The device of claim 17 , wherein the isolation structure is further positioned laterally between the first gate section and the drain region and extends into the first well region within the semiconductor layer, and
wherein the device further comprises an additional gate sidewall spacer on the isolation structure positioned laterally adjacent to the additional gate conductor layer.

19 . The device of claim 14 , wherein the first gate dielectric layer includes an insulator layer, wherein the first gate conductor layer includes a monocrystalline semiconductor layer, and wherein the additional gate conductor layer includes an additional monocrystalline semiconductor layer.

20 . A method including:
providing a semiconductor layer; and forming a device including:
a gate including:
a first gate section including: a first gate dielectric layer on the semiconductor layer; and a first gate conductor layer on the first gate dielectric layer; and
a second gate section including: a second gate dielectric layer on the semiconductor layer and further extending onto the first gate conductor layer; and a second gate conductor layer on the second gate dielectric layer, wherein the second gate dielectric layer is thinner than the first gate dielectric layer;

a gate sidewall spacer on the first gate conductor layer of the first gate section and positioned laterally adjacent the second gate dielectric layer and the second gate conductor layer of the second gate section; and
an isolation structure positioned laterally immediately adjacent to the first gate d

Assignees

• Globalfoundries Us Inc

Inventors

• Melde Thomas
• Richter Ralf
• Dünkel Stefan

Classifications

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title