LDMOS with improved breakdown voltage and with non-uniformed gate dielectric and gate electrode

Patent metadata

Field	Value
Publication number	US-10032902-B2
Application number	US-201514713819-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	Mar 11, 2011
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

First claim

What is claimed is:

1. A lateral diffused MOS (LDMOS) device comprising:
a substrate;
a p − well and a n − Epi well in the substrate, the n − Epi well surrounding the p − well;
a source in the p − well and a drain in the n − Epi well;
a p + dopant in the p − well, the p+ dopant functioning as a body contact to the p − well;
a first gate stack on a portion of the p − well;
a second gate stack on a portion of the n − Epi well, the first and second gate stacks having a common metal gate electrode;
an interlayer dielectric (ILD) over the entire substrate, having a cavity formed over the portion of the p − well and the portion of the n − Epi well;
a first dielectric layer comprising HfSiON/La 2 O 3 formed in the cavity on the portion of the first well; and
a second dielectric layer comprising HfSiON/titanium nitride (TiN)/aluminum (Al)/TiN formed in the cavity on the portion of the second well,
wherein the work function of the second gate stack is higher than the work function of the first gate stack, and
the common metal gate electrode formed on the first and second dielectric layers.

2. A device comprising:
a substrate;
a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;
a source in the first well and a drain in the second well;
a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;
a first gate stack over a portion of the first well; and
a second gate stack over a portion of the second well, the first and second gate stacks comprising: a dielectric layer on the portion of the first well and on the portion of the second well,
wherein the first and second gate stacks have a common gate electrode,
a work function of the second gate stack is higher than the work function of the first gate stack, and
the dielectric layer on the portion of the second well further comprises Ti/Ni annealed to an upper surface of the dielectric layer on the portion of the second well.

3. The device according to claim 2 , shallow trench isolation regions (STI) formed at opposite sides of the common gate electrode.

4. The device according to claim 2 , wherein the second well comprises an n − Epi well and the first well comprises a p − well.

5. The device according to claim 2 , wherein the dielectric layer on the portion of the first well comprises HfSiON/La 2 O 3 .

6. The device according to claim 5 , wherein the dielectric layer on the portion of the second well comprises HfSiON/TiN/Al/TiN.

7. A device comprising:
a substrate;
a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well;
a source in the first well and a drain in the second well;
a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well;
a first gate stack on a portion of the first well;
a second gate stack on a portion of the second well, the first and second gate stacks having a common metal gate electrode;
an interlayer dielectric (ILD) over the entire substrate, having a cavity formed over the portion of the first well and the portion of the second well;
a first dielectric layer in the cavity on the portion of the first well; and
a second dielectric layer in the cavity on the portion of the second well,
wherein the work function of the second gate stack is higher than the work function of the first gate stack,
wherein the first dielectric layer comprises HfSiON/La 2 O 3 and the second dielectric layer comprises HfSiON/titanium nitride (TiN)/aluminum (Al)/TiN, and
the common metal gate electrode formed on the first and second dielectric layers.

8. The device according to claim 7 , the first and second gate stacks comprising:
a first high-k dielectric layer on the portion of the first well;
a second high-k dielectric layer on the portion of the second well; and
a common gate electrode on both the first and second high-k dielectric layers.

9. The device according to claim 7 , the first and second gate stacks comprising:
a dielectric layer on the portion of the first well and on the portion of the second well;
a first dopant implanted in the dielectric layer on the portion of the first well; and
a second dopant, different from the first dopant, implanted in the dielectric layer on the portion of the second well; and
a common gate electrode on the dielectric layer.

10. The device according to claim 7 , further comprising:
an interlayer dielectric (ILD) over the entire substrate, having a cavity formed over the portion of the first well and the portion of the second well;
a dielectric layer in the cavity on the portion of the first well and the portion of the second well;
a first dopant implanted in the dielectric layer on the portion of the first well;
a second dopant, different from the first dopant, implanted in the dielectric layer on the portion of the second well; and
a common metal gate on the dielectric layer.

11. The device according to claim 7 , further comprising:
an interlayer dielectric (ILD) over the entire substrate, having a cavity formed over the portion of the first well and the portion of the second well;
a dielectric layer in the cavity;
a work function adjustment material deposited on the dielectric layer on the portion of the first well or the portion of the second well; and
a common metal gate on the dielectric layer and on the work function adjustment material.

12. The device according to claim 7 , further comprising shallow trench isolation regions (STI) formed at opposite sides of the common gate electrode.

13. The device according to claim 7 , wherein the second well comprises an n − Epi well and the first well comprises a p − well.

14. The device according to claim 7 , the first and second gate stacks comprising:
an oxide layer on the portion of the second well;
a high-k dielectric layer on the portion of the first well and on the oxide layer; and
a common metal gate electrode on the high-k dielectric layer.

15. The device according to claim 14 , wherein the high-k dielectric layer is selected from hafnium silicon oxynitride (HfSiON) or silicon dioxide (SiO 2 )/HfSiON.

16. The device according to claim 7 , the first and second gate stacks comprising:
a dielectric layer on the portion of the first well and on the portion of the second well;
a work function adjustment material deposited on the dielectric layer on the portion of the first well or the portion of the second well; and
a common gate electrode on the dielectric layer.

17. The device according to claim 16 , wherein the work function adjustment material comprises lanthanum oxide (La 2 O 3 ).

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Toh Eng Huat
• Lee Jae Gon
• Tan Chung Foong
• Quek Elgin

Classifications

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H01L29/66681

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/7816 Primary

  Electricity · mapped topic