Electronic apparatus minimizing differential thermal contraction for cryogenic quantum computers

Patent metadata

Field	Value
Publication number	US-12557210-B2
Application number	US-202218053167-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Nov 7, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

One or more devices and/or methods provided herein relate to a method for fabricating a filtering electronic device having a co-integrated impedance modification element and signal transmission line. An electronic structure can comprise a circuit board, and a first plate and a second plate retaining the circuit board therebetween, wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is lower than a cryogenic thermal contraction rate of the circuit board. In one or more embodiments, a silicon chip can be physically coupled to the circuit board by a plurality of solder bumps and disposed between the first plate and the second plate.

First claim

What is claimed is:

1 . An electronic structure comprising:
a circuit board; a first plate and a second plate retaining the circuit board therebetween, wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is lower than a cryogenic thermal contraction rate of the circuit board; a silicon chip received into a recess of the circuit board; and fasteners extending through the first plate and the second plate to thereby maintain the silicon chip within the recess of the circuit board, wherein the plurality of fasteners comprise a first plurality of fasteners extending through at least a pair of layers of only the first plate to couple together the at least a pair of layers of the first plate, or a plurality of second fasteners extending through at least a pair of layers of only the second plate to couple together the at least a pair of layers of the second plate.

2 . The electronic structure of claim 1 , wherein the silicon chip is physically coupled to the circuit board by a plurality of solder bumps disposed between the first plate and the second plate.

3 . The electronic structure of claim 2 , wherein a second silicon chip is physically coupled to the silicon chip by a plurality of solder bumps and is retained between the first plate and the second plate.

4 . The electronic structure of claim 1 , wherein at least one of the first plate or the second plate comprises a plurality of layers comprising at least a first layer comprising molybdenum and a second layer comprising copper.

5 . The electronic structure of claim 4 , wherein a pair of layers of the plurality of layers are explosion welded to one another.

6 . The electronic structure of claim 4 , wherein the second layer is electroplated to the first layer, and wherein the second layer comprises molybdenum and has a thickness in a range of 3 millimeters to 6 millimeters.

7 . The electronic structure of claim 1 , wherein the plurality of fasteners extend through the first plate and the second plate and couple the first plate and the second plate towards one another and towards the silicon chip.

8 . The electronic structure of claim 1 , wherein at least the first plate or the second plate has a cryogenic thermal contraction rate that is a factor of at least 0.5 lower than a cryogenic thermal contraction rate of the circuit board.

9 . The electronic structure of claim 1 , wherein each of the first plate and the second plate comprises at least three layers comprising a first layer, a second layer, and a middle layer disposed between the first layer and the second layer, and wherein the first layers comprise one of molybdenum or copper, the second layers comprise the same one of molybdenum or copper as the first layers, and the middle layers comprises the other of molybdenum or copper.

10 . The electronic structure of claim 9 , wherein a thickness of the middle layers of the first plate and the second plate, in a direction extending normally between the respective first layers and second layers, is at least a third less thick than each of the first layers and second layers, and wherein only the middle layers comprise the copper.

11 . A method for fabricating an electronic structure by a fabrication system, the method comprising:
coupling, by the fabrication system, a silicon chip to a circuit board; and coupling, by the fabrication system, a first plate and a second plate to the circuit board with the circuit board and the silicon chip being retained between the first plate and the second plate, wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is lower than a cryogenic thermal contraction rate of the circuit board, wherein a cryogenic thermal contraction rate of the silicon chip is less than the cryogenic thermal contraction rate of each of the first plate and the second plate, and wherein at least one of the first plate or the second plate comprises a second layer electroplated to a first layer, wherein the second layer comprises molybdenum and has a thickness in a range of 3 millimeters to 6 millimeters.

12 . The method according to claim 11 , wherein the coupling of the silicon chip to the circuit board comprises using a plurality of solder bumps to physically couple the silicon chip to the circuit board.

13 . The method according to claim 11 , further comprising:
coupling together, by the fabrication system, at least a pair of layers of the first plate by a first plurality of fasteners, or coupling together, by the fabrication system, at least a pair of layers of the second plate by a second plurality of fasteners.

14 . An electronic structure, comprising:
a circuit board; a silicon chip physically coupled to the circuit board by a plurality of solder bumps; and a first plate and a second plate retaining the circuit board and the silicon chip therebetween, wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is lower than a cryogenic thermal contraction rate of the circuit board, wherein a cryogenic thermal contraction rate of the silicon chip is less than the cryogenic thermal contraction rate of each of the first plate and the second plate, and wherein at least one of the first plate or the second plate comprises a second layer electroplated to a first layer, wherein the second layer comprises molybdenum and has a thickness in a range of 3 millimeters to 6 millimeters.

15 . The electronic structure of claim 14 , wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is at least a factor of 0.5 lower than a cryogenic thermal contraction rate of the circuit board.

16 . The electronic structure of claim 14 , wherein the first plate and the second plate each have a cryogenic thermal contraction rate that is at least a factor of 4 higher than a cryogenic thermal contraction rate of the silicon chip.

17 . The electronic structure of claim 1 , wherein the silicon chip comprises a qubit chip.

18 . The method according to claim 11 , further comprising:
aligning, by the fabrication system, the silicon chip within a recess of the circuit board.

19 . The electronic structure of claim 14 , wherein the silicon chip comprises a qubit chip.

Assignees

• IBM

Inventors

• Hall Shawn Anthony
• Beckley Michael Justin
• Cotte John Michael

Classifications

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H05K7/20372 Primary

  Cryogenic cooling; Nitrogen liquid cooling · CPC title

• H05K2201/09072

  Hole or recess under component or special relationship between hole and component · CPC title

• H05K2201/10378

  Interposers · CPC title

• H05K2201/2018

  Presence of a frame in a printed circuit or printed circuit assembly · CPC title