Quantum computing assemblies

Patent metadata

Field	Value
Publication number	US-10380496-B2
Application number	US-201815925594-A
Country	US
Kind code	B2
Filing date	Mar 19, 2018
Priority date	Mar 19, 2018
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.

First claim

The invention claimed is:

1. A quantum computing assembly, comprising:
a package substrate having a first surface and an opposing second surface;
a first die having a first surface and an opposing second surface, wherein the first surface of the first die is coupled to the second surface of the package substrate by first interconnects, and the first surface of the first die is at least partially between the second surface of the package substrate and the second surface of the first die; and
a second die having a first surface and an opposing second surface, wherein the first surface of the second die is coupled to the second surface of the package substrate by second interconnects, and the first surface of the second die is at least partially between the second surface of the package substrate and the second surface of the second die;
wherein the first die or the second die includes quantum processing circuitry, and the first die is coupled to the second die by lateral interconnects; and
wherein (1) at least one of the lateral interconnects couples the second surface of the first die to the second surface of the second die, and the first die includes qubit elements located closer to the second surface of the first die than to the first surface of the first die; or (2) at least one of the lateral interconnects couples the first surface of the first die to the first surface of the second die, and the first die includes qubit elements located closer to the first surface of the first die than to the second surface of the first die.

2. The quantum computing assembly of claim 1 , wherein the second surface of the package substrate includes one or more cavities.

3. The quantum computing assembly of claim 2 , wherein at least one of the cavities is under at least one of the lateral interconnects.

4. The quantum computing assembly of claim 1 , wherein the lateral interconnects include a superconductor.

5. The quantum computing assembly of claim 1 , wherein at least one of the lateral interconnects includes at least three sub-interconnects.

6. The quantum computing assembly of claim 1 , wherein at least one of the lateral interconnects has a serpentine footprint.

7. A quantum computing assembly, comprising:
a package substrate having a first surface and an opposing second surface;
a first die having a first surface and an opposing second surface, wherein the second surface of the first die is coupled to the second surface of the package substrate by first interconnects, and the first surface of the first die is at least partially between the second surface of the package substrate and the second surface of the first die; and
a second die having a first surface and an opposing second surface, wherein the second surface of the second die is coupled to the second surface of the package substrate by second interconnects, and the first surface of the second die is at least partially between the second surface of the package substrate and the second surface of the second die;
wherein the first die or the second die includes quantum processing circuitry, and the first die is coupled to the second die by lateral interconnects; and
wherein (1) at least one of the lateral interconnects couples the second surface of the first die to the second surface of the second die, and the first die includes qubit elements located closer to the second surface of the first die than to the first surface of the first die; or (2) at least one of the lateral interconnects couples the first surface of the first die to the first surface of the second die, and the first die includes qubit elements located closer to the first surface of the first die than to the second surface of the first die.

8. The quantum computing assembly of claim 7 , wherein the quantum processing circuitry includes superconducting qubit elements.

9. The quantum computing assembly of claim 7 , wherein the quantum processing circuitry includes a quantum well stack and a plurality of gates above the quantum well stack.

10. The quantum computing assembly of claim 7 , wherein the lateral interconnects include an air bridge.

11. The quantum computing assembly of claim 7 , wherein the first interconnects and the second interconnects include wirebonds and the wirebonds include a superconductor.

12. The quantum computing assembly of claim 7 , wherein at least one of the lateral interconnects includes a wirebond and the wirebond includes a superconductor.

13. A quantum computing assembly, comprising:
a plurality of dies electrically coupled to a surface of a package substrate; and
lateral interconnects between different dies of the plurality of dies;
wherein the lateral interconnects include a superconductor, at least one of the dies of the plurality of dies includes quantum processing circuitry, and the surface of the package substrate includes one or more cavities.

14. The quantum computing assembly of claim 13 , wherein the plurality of dies includes three or more dies.

15. The quantum computing assembly of claim 13 , wherein the plurality of dies are electrically coupled to the surface of the package substrate by solder interconnects between the plurality of dies and the package substrate, and the solder interconnects include a superconductor.

16. The quantum computing assembly of claim 13 , wherein the plurality of dies are electrically coupled to the surface of the package substrate by wirebonds, and the wirebonds include a superconductor.

17. A quantum computing assembly, comprising:
a package substrate having a first surface and an opposing second surface;
a first die having a first surface and an opposing second surface, wherein the first die is coupled to the second surface of the package substrate by first interconnects, and the first surface of the first die is at least partially between the second surface of the package substrate and the second surface of the first die; and
a second die having a first surface and an opposing second surface, wherein the second die is coupled to the second surface of the package substrate by second interconnects, and the first surface of the second die is at least partially between the second surface of the package substrate and the second surface of the second die;
wherein the first die or the second die includes quantum processing circuitry, the first die is coupled to the second die by lateral interconnects, and the second surface of the package substrate includes one or more cavities.

18. The quantum computing assembly of claim 17 , wherein at least one of the cavities is under at least one of the lateral interconnects.

19. The quantum computing assembly of claim 17 , wherein (1) at least one of the lateral interconnects couples the second surface of the first die to the second surface of the second die, and the first die includes qubit elements located closer to the second surface of the first die than to the first surface of the first die; or (2) at least one of the lateral interconnects couples the first surface of the first die to the first surface of the second die, and the first die includes qubit elements located closer to the first surface of the first die than to the second surface of the first die.

20. The quantum computing assembly of claim 17 , wherein the lateral interconnects include an air bridge or a wirebond.

21. The quantum computing assembly of claim 17 , wherein at least one of the lateral interconnects includes at least three sub-interconnects.

22. The quantum computing assemb

Assignees

• Intel Corp

Inventors

• Elsherbini Adel A
• Falcon Javier A
• George Hubert C
• Liff Shawna M
• Clarke James S

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title