Multi-channel decoder with distributed scheduling

Patent metadata

Field	Value
Publication number	US-12556200-B2
Application number	US-202318509221-A
Country	US
Kind code	B2
Filing date	Nov 14, 2023
Priority date	Nov 20, 2018
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.

First claim

What is claimed is:

1 . A multi-channel decoder circuit, comprising:
a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords; and a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to a respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, wherein when distributing each incoming codeword of the one or more codewords, the distribution controller is to select the respective unit decoder circuit of the set of unit decoder circuits based on a power metric.

2 . The multi-channel decoder circuit of claim 1 , wherein the distribution controller circuit comprises:
a controller circuit configured to:
identify an arrival of each incoming codeword of the plurality of codewords associated with the plurality of input channels; and
determine a currently available unit decoder circuit within the set of unit decoder circuits to distribute each of the respective incoming codeword.

3 . The multi-channel decoder circuit of claim 2 , wherein the distribution controller circuit further comprises:
an input distribution network circuit configured to distribute each incoming codeword of the plurality of codewords associated with a plurality of input channels to the respective unit decoder circuit, based on instructions from the controller circuit; and an output distribution network circuit configured to distribute decoded codewords from the set of unit decoder circuits to a plurality of output channels associated therewith, based on instructions from the controller circuit.

4 . The multi-channel decoder circuit of claim 2 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises determining that the unit decoder circuit within the set of unit decoder circuits is free to decode the incoming codeword.

5 . The multi-channel decoder circuit of claim 2 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining that the unit decoder circuit within the set of unit decoder circuits that is decoding the codeword that has a different QoS class than the incoming codeword; and stopping the decoding of the codeword with the lower QoS class, to make the unit decoder circuit available for the incoming codeword.

6 . The multi-channel decoder circuit of claim 2 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining that the unit decoder circuit within the set of unit decoder circuits has exceeded the maximum delay assigned for processing a current codeword that the unit decoder circuit is processing; and stopping the decoding of the current codeword, to make the unit decoder circuit available for the incoming codeword.

7 . The multi-channel decoder circuit of claim 1 , wherein the set of unit decoder circuits are arranged into two or more decoder pool circuits, each decoder pool circuit comprising one or more unit decoder circuits with a predefined QoS class.

8 . The multi-channel decoder circuit of claim 7 , wherein the distribution controller circuit is configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit, based on determining the QoS class of the incoming codeword and based on determining that a currently available unit decoder circuit within the decoder pool circuit has the corresponding QoS class.

9 . The multi-channel decoder circuit of claim 1 , further comprising a dedicated decoder circuit coupled to the distribution controller circuit, and configured to process the plurality of codewords associated with the plurality of input channels, prior to providing the plurality of codewords to the distribution controller circuit,
wherein the dedicated decoder circuit comprises a plurality of unit channel decoder circuits each associated with a respective input channel of the plurality of input channels, wherein each of the plurality of unit channel decoder circuits is configured to process codewords associated with a respective input channel of the plurality of input channels, thereby providing a plurality of processed codewords.

10 . The multi-channel decoder circuit of claim 1 , wherein a number of unit decoder circuits within the set of unit decoder circuits is less than a number of input channels within the plurality of input channels.

11 . The multi-channel decoder circuit of claim 1 , wherein the multi-channel decoder circuit is associated with digital subscriber line (xDSL) systems.

12 . A method for a multi-channel decoder circuit, comprising:
receiving one or more codewords of a plurality of codewords associated with a plurality of input channels; and distributing each incoming codeword of the one or more codewords to a respective unit decoder circuit of a set of unit decoder circuits, wherein distributing each incoming codeword of the one or more codewords comprises selecting the respective unit decoder circuit of the set of unit decoder circuits based on a power metric.

13 . The method of claim 12 , wherein distributing each incoming codeword of the one or more codewords to a respective unit decoder circuit of a set of unit decoder circuits includes determining a currently available unit decoder circuit within the set of unit decoder circuits.

14 . The method of claim 12 , wherein determining a currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining a unit decoder circuit within the set of unit decoder circuits that is decoding a codeword that has a lower QoS class than the incoming codeword; and stopping the decoding of the codeword with the lower QoS class, in order to make the unit decoder circuit available for the incoming codeword.

15 . The method of claim 12 , wherein determining a currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining a unit decoder circuit within the set of unit decoder circuits that has exceeded the maximum delay assigned for processing a current codeword that the unit decoder circuit is processing; and stopping the decoding of the current codeword, in order to make the unit decoder circuit available for the incoming codeword.

16 . The method of claim 12 , wherein the set of unit decoder circuits are arranged into two or more decoder pool circuits, each decoder pool circuit comprising one or more unit decoder circuits with a predefined QoS class.

17 . The method of claim 12 , wherein a number of unit decoder circuits within the set of unit decoder circuits is less than a number of input channels within the plurality of input channels.

18 . The method of claim 12 , wherein a number iterations to process the one or more codewords is greater than 1.

19 . The method of claim 12 , wherein distributing each incoming codeword of the one or more codewords to a respective unit decoder circuit of a set of unit decoder circuits includes:
determining that the unit decoder circuit within the set of unit decoder circuits that is decoding the codeword that has a different QoS class than the incoming codeword; and stopping the decoding of the codeword with the lower QoS class, to make the unit decoder circuit available for the incom

Assignees

• Maxlinear Inc

Inventors

• Schedelbeck Gert
• Uhlemann Stefan

Classifications

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/1117

  using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title