Multi-channel decoder with distributed scheduling

Patent metadata

Field	Value
Publication number	US-11817878-B2
Application number	US-201816196422-A
Country	US
Kind code	B2
Filing date	Nov 20, 2018
Priority date	Nov 20, 2018
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.

First claim

What is claimed is:

1. A multi-channel decoder circuit, comprising:
a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and iteratively decode the one or more codewords, a number of iterations being based on a latency target; and
a distribution controller circuit configured to distribute an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on a predefined condition, the predefined condition relating to a quality-of-service (QoS) class of the incoming codeword, the plurality of codewords being distributed based on determining a currently available unit decoder circuit within the set of unit decoder circuits and based on the respective QoS class, a particular codeword being distributed specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.

2. The multi-channel decoder circuit of claim 1 , wherein the distribution controller circuit comprises:
a controller circuit configured to:
identify an arrival of the incoming codeword of the plurality of codewords associated with the plurality of input channels; and
determine the currently available unit decoder circuit within the set of unit decoder circuits, in order to distribute each of the respective incoming codeword.

3. The multi-channel decoder circuit of claim 2 , wherein the distribution controller circuit further comprises:
an input distribution network circuit configured to distribute the incoming codeword of the plurality of codewords associated with a plurality of input channels to a respective unit decoder circuit, based on instructions from the controller circuit; and
an output distribution network circuit configured to distribute decoded codewords from the set of unit decoder circuits to a plurality of output channels associated therewith, based on instructions from the controller circuit.

4. The multi-channel decoder circuit of claim 1 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises determining a unit decoder circuit within the set of unit decoder circuits that is free to decode the incoming codeword.

5. The multi-channel decoder circuit of claim 1 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining a unit decoder circuit within the set of unit decoder circuits that is decoding a codeword that has a lower QoS class than the incoming codeword; and
stopping the decoding of the codeword with the lower QoS class, in order to make the unit decoder circuit available for the incoming codeword.

6. The multi-channel decoder circuit of claim 1 , wherein determining the currently available unit decoder circuit within the set of unit decoder circuits comprises:
determining a unit decoder circuit within the set of unit decoder circuits that has exceeded the maximum delay assigned for processing a current codeword that the unit decoder circuit is processing; and
stopping the decoding of the current codeword, in order to make the unit decoder circuit available for the incoming codeword.

7. The multi-channel decoder circuit of claim 1 , wherein the set of unit decoder circuits are arranged into two or more decoder pool circuits, each decoder pool circuit comprising one or more unit decoder circuits with a predefined QoS class.

8. The multi-channel decoder circuit of claim 7 , wherein the distribution controller circuit is configured to distribute the incoming codeword of the one or more codewords to the respective unit decoder circuit, based on determining the QoS class of the incoming codeword and based on determining the currently available unit decoder circuit within a decoder pool circuit with a corresponding QoS class.

9. The multi-channel decoder circuit of claim 1 , further comprising a dedicated decoder circuit coupled to the distribution controller circuit, and configured to process the plurality of codewords associated with the plurality of input channels, prior to providing the plurality of codewords to the distribution controller circuit, wherein the dedicated decoder circuit comprises a plurality of unit channel decoder circuits each associated with a respective input channel of the plurality of input channels, wherein each of the plurality of unit channel decoder circuits is configured to process codewords associated with a respective input channel of the plurality of input channels, thereby providing a plurality of processed codewords.

10. The multi-channel decoder circuit of claim 1 , wherein a number of unit decoder circuits within the set of unit decoder circuits is less than a number of input channels within the plurality of input channels.

11. The multi-channel decoder circuit of claim 1 , wherein the multi-channel decoder circuit is associated with digital subscriber line (xDSL) systems.

12. The multi-channel decoder circuit of claim 1 , wherein a number iterations to process the one or more codewords is greater than 1.

13. A multi-channel decoder system, comprising: a multi-channel decoder circuit comprising:
a distributed decoder circuit comprising a set of unit decoder circuits distributed between at least two separate hardware devices, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords; and
a distribution controller circuit configured to distribute an incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits, based on determining a currently available unit decoder circuit within the set of unit decoder circuits and based on a capability of the currently available unit decoder circuit to decode a particular codeword, the capability relating to a predefined condition, and based on a respective predefined quality-of-service (QoS) class for the incoming codeword, the particular codeword being distributed specifically to the currently available unit decoder circuit based on a particular QoS class for the particular codeword.

14. The multi-channel decoder system of claim 13 , wherein the distribution controller circuit comprises:
a controller circuit configured to:
identify an arrival of the incoming codeword of the plurality of codewords associated with the plurality of input channels; and
determine the currently available unit decoder circuit within the set of unit decoder circuits, in order to distribute each of the respective incoming codeword.

15. The multi-channel decoder system of claim 14 , wherein the distribution controller circuit further comprises:
an input distribution network circuit configured to distribute the incoming codeword of the plurality of codewords associated with the plurality of input channels to a respective unit decoder circuit, based on instructions from the controller circuit; and
an output distribution network circuit configured to distribute decoded codewords from the set of unit decoder circuits to a respective plurality of output channels associated therewith.

16. The multi-channel decoder system of claim 15 , further comprising an input buffer circuit comprising a plurality of unit input buffer circuits configured to store incoming codewords associated with a respective input channel of the plurality of input ch

Assignees

• Maxlinear Inc

Inventors

• Schedelbeck Gert
• Uhlemann Stefan

Classifications

• H03M13/114 Primary

  Shuffled, staggered, layered or turbo decoding schedules · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H03M13/3707

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/6502 Primary

  Reduction of hardware complexity or efficient processing · CPC title