Driver circuit for light emitting modules with combined active and passive matrix functionalities

US12555525B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12555525-B2
Application numberUS-202218572232-A
CountryUS
Kind codeB2
Filing dateJun 30, 2022
Priority dateJun 30, 2021
Publication dateFeb 17, 2026
Grant dateFeb 17, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A driver circuit for driving a matrix of N×M pixels of a light emitting module. Each pixel is composed of at least three types of light emitting elements. The light emitting elements are driven by a modulation control signal. The driver circuit is embedded in a TFT layer. It is configured to cooperate with N multiplexers provided in an external driver circuit, each multiplexer being configured to drive one line of M pixels. It is also configured to cooperate with one external current source per type of light emitting element, each external current source being mirrored M times on the matrix of the driver circuit and being arranged in series with a signal switch for generating the control signal provided for each of the M columns.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A driver circuit for driving a matrix of N×M pixels of a light emitting module, wherein each pixel is composed of at least three types of light emitting elements, the light emitting elements being driven by a modulation control signal of period T configured to switch the light emitting elements on and off at most during 1/Nth of the period T, wherein the period T corresponds to the duration of a frame, and wherein the driver circuit is embedded in a thin-film transistor (TFT) layer such that a switch is embedded in each light emitting element, and is configured to cooperate with N multiplexers provided in an external driver circuit, each multiplexer being configured to drive a respective line of M pixels, and the combination of multiplexers is configured to address all the pixels of the N×M matrix during one period of the modulation control signal, and each pixel of a group of M pixels is shown consecutively during at most 1/Nth of the period T, at least one external current source per type of light emitting element to drive the N×M matrix, and wherein each external current source is mirrored M times on the TFT layer of the driver circuit and is arranged in series with a modulation control signal switch for generating the modulation control signal provided for each of the M columns of the matrix. 2 . The driver circuit according to claim 1 wherein the modulation control signal is a pulse width modulation signal, and the modulation control signal switch is a pulse width modulation switch. 3 . The driver circuit according to claim 1 , wherein the three types of light emitting elements emit a different color, wherein the different colors are at least red, green, and blue. 4 . The driver circuit according to claim 1 , wherein the external current sources are provided on a printed circuit board (PCB) arranged under the matrix. 5 . The driver circuit according to claim 1 , wherein the multiplexers are provided on a printed circuit board (PCB) arranged under the matrix. 6 . The driver circuit according to claim 1 , wherein the multiplexers are transistors implemented with a low drain-source on-resistance field effect transistor (Rds(on) FET). 7 . The driver circuit according to claim 1 , wherein the lines of the multiplexers for addressing the pixels are such that one line for addressing the pixels comprises pixels of different rows. 8 . The driver circuit according to claim 1 , wherein the lines of the multiplexers for addressing the pixels are such that at least two pixels in the same column are addressed by the same line. 9 . The driver circuit according to claim 1 , wherein the order in which the multiplexers are addressed is not linear. 10 . The driver circuit according to claim 1 , wherein the pixels are addressed several times during one frame. 11 . The driver circuit according to claim 1 , wherein colors of sub-pixels composing a pixel are at least red, green, blue, and may further comprise any one of red, green, blue, white, yellow, cyan, magenta or any other color. 12 . The driver circuit according to claim 1 , wherein the light emitting elements are any one of light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QD-LEDs), electroluminescent quantum light-emitting diodes (EL-QLEDs), active-matrix organic light-emitting diodes (AMOLEDs), mini-LEDs, micro-LEDs. 13 . The driver circuit according to claim 1 , wherein the light emitting elements are provided with quantum dots to generate the different colors of emission. 14 . A chip configured to cooperate with the driver circuit of claim 2 , the chip comprising N multiplexers, each multiplexer being configured to drive one line of M pixels, and the combination of multiplexers being configured to address all the pixels of the N×M matrix during one period of the Pulse Width Modulated signal. 15 . A chip configured to cooperate with the driver circuit of claim 1 , the chip comprising one current source per sub-pixel to drive the N×M matrix, said current source being mirrored M times on the TFT layer and arranged in series with a PWM switch provided in each of the M columns of the matrix. 16 . A chip configured to cooperate with the driver circuit and comprising the chip of claim 14 and a chip comprising one current source per sub-pixel to drive the N×M matrix, said current source being mirrored M times on the thin-film transistor (TFT) layer and arranged in series with a pulse width modulation (PWM) switch provided in each of the M columns of the matrix. 17 . A light emitting module comprising a matrix of N×M pixels, at least one driver circuit associated to said matrix according to claim 1 , and for each driver circuit and associated matrix, a chip configured to cooperate with the driver circuit, the chip comprising N multiplexers, each multiplexer being configured to drive one line of M pixels, and the combination of multiplexers being configured to address all the pixels of the N×M matrix during one period of the Pulse Width Modulated signal and a chip configured to cooperate with the driver circuit, the chip comprising one current source per sub-pixel to drive the N×M matrix, said current source being mirrored M times on the thin-film transistor (TFT) layer and arranged in series with a pulse width modulation (PWM) switch provided in each of the M columns of the matrix. 18 . A display module comprising at least one light emitting module according to claim 17 . 19 . A tiled display comprising at least one display module according to claim 18 .

Assignees

Inventors

Classifications

  • Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions · CPC title

  • semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

  • by modulation of the duration of a single pulse during which the logic level remains constant · CPC title

  • G09G3/3216Primary

    using a passive matrix · CPC title

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What does patent US12555525B2 cover?
A driver circuit for driving a matrix of N×M pixels of a light emitting module. Each pixel is composed of at least three types of light emitting elements. The light emitting elements are driven by a modulation control signal. The driver circuit is embedded in a TFT layer. It is configured to cooperate with N multiplexers provided in an external driver circuit, each multiplexer being configured …
Who is the assignee on this patent?
Barco Nv
What technology area does this patent fall under?
Primary CPC classification G09G3/3216. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 17 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).