Application programming interface to indicate thread blocks

Patent metadata

Field	Value
Publication number	US-12554534-B2
Application number	US-202217955023-A
Country	US
Kind code	B2
Filing date	Sep 28, 2022
Priority date	Jul 29, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate two or more blocks of threads to be scheduled in parallel.

First claim

What is claimed is:

1 . A processor comprising:
one or more circuits to perform an application programming interface (API) to indicate two or more groups of blocks of threads of a software kernel to be performed on a graphics processing unit (GPU), wherein the API is to indicate the two or more groups of blocks of threads by indicating one or more dimensions of the groups of blocks of threads.

2 . The processor of claim 1 , wherein the one or more circuits are to further cause the API to indicate that the two or more groups of blocks of threads are scheduled in parallel.

3 . The processor of claim 1 , wherein the one or more circuits are to further cause the API to indicate the two or more groups of blocks of threads by setting a dimension of a group of blocks of threads, of the two or more groups of blocks of threads, to be performed in parallel.

4 . The processor of claim 1 , wherein a group of blocks of threads is in a partition of blocks of a grid of threads, wherein the partition is a partition among multiple partitions of the blocks of the grid of threads.

5 . The processor of claim 1 , wherein the one or more circuits are to further indicate the two or more groups of blocks of threads by indicating how the two or more groups of blocks of threads are indexed.

6 . The processor of claim 1 , wherein the one or more circuits are to perform the API to indicate the two or more groups of blocks of threads by indicating at least one of at least three dimensions of a partition of multiple partitions of blocks of threads of the software kernel.

7 . The processor of claim 1 , wherein the one or more circuits are to perform the API to indicate the two or more groups of blocks of threads by indicating a property of the kernel.

8 . The processor of claim 1 , wherein the two or more groups of blocks of threads are distributed among multiple multiprocessors to be scheduled in parallel.

9 . The processor of claim 1 , wherein the two or more groups of blocks of threads are a cluster of one or more clusters of two or more groups of blocks of threads separately manageable using one or more other APIs.

10 . A computer-implemented method comprising:
receiving an application programming interface (API) call comprising one or more parameters indicative of one or more dimensions of two or more groups of blocks of threads of a software kernel to be performed by a graphics processing unit (GPU); and in response to receiving the API call, causing the two or more groups of blocks of threads to be scheduled to be performed in parallel.

11 . The computer-implemented method of claim 10 , further comprising indicating, in response to receiving the API call, one or more dimensions of the groups of blocks of threads.

12 . The computer-implemented method of claim 10 , further comprising setting, in response to receiving the API call, a dimension of a group of blocks of threads, of the two or more groups of blocks of threads, to be performed in parallel.

13 . The computer-implemented method of claim 10 , wherein a group of blocks of threads is in a partition of blocks of a grid of threads, wherein the partition is a partition among multiple partitions of the blocks of the grid of threads.

14 . The computer-implemented method of claim 10 , further indicating, in response to receiving the API call, how the two or more groups of blocks of threads are indexed.

15 . The computer-implemented method of claim 10 , further comprising indicating, in response to receiving the API call, at least one of at least three dimensions of a partition of multiple partitions of blocks of threads of a software kernel.

16 . The computer-implemented method of claim 10 , further comprising indicating, in response to receiving the API call, a property of two or more groups of blocks of threads.

17 . The computer-implemented method of claim 10 , wherein the two or more groups of blocks of threads are distributed among multiple multiprocessors to be performed in parallel.

18 . The computer-implemented method of claim 10 , wherein the two or more groups of blocks of threads are a cluster of one or more clusters of two or more groups of blocks of threads separately manageable using one or more other APIs.

19 . A computer system comprising:
one or more processors and memory storing executable instructions that, when performed by the one or more processors, are to perform an application programming interface (API) to indicate two or more groups of blocks of threads of a software kernel to be performed on a graphics processing unit (GPU), wherein the API is to indicate the two or more groups of blocks of threads by indicating one or more dimensions of the groups of blocks of threads.

20 . The computer system of claim 19 , wherein the one or more processors are to further indicate that the two or more groups of blocks of threads are scheduled in parallel.

21 . The computer system of claim 19 , wherein the one or more processors, are to further indicate the two or more groups of blocks of threads by setting a dimension of a group of blocks of threads, of the two or more groups of blocks of threads, to be performed in parallel.

22 . The computer system of claim 19 , wherein a group of blocks of threads is in a partition of blocks of a grid of threads, wherein the partition is a partition among multiple partitions of the blocks of the grid of threads.

23 . The computer system of claim 19 , wherein the one or more processors are to further indicate the two or more groups of blocks of threads by indicating how the two or more groups of blocks of threads are indexed.

24 . The computer system of claim 19 , wherein the one or more processors are to further indicate the two or more groups of blocks of threads by indicating at least one of at least three dimensions of a partition of multiple partitions of blocks of threads of the software kernel.

25 . The computer system of claim 19 , wherein the one or more processors, are to further indicate the two or more groups of blocks of threads by indicating a property of the kernel.

26 . The computer system of claim 19 , wherein the two or more groups of blocks of threads are to be distributed among multiple multiprocessors to be scheduled in parallel.

27 . The computer system of claim 19 , wherein the two or more groups of blocks of threads are a cluster of one or more clusters of two or more groups of blocks of threads separately manageable using one or more other APIs.

28 . A non-transitory machine-readable medium having stored thereon a set of instructions, that when performed by one or more processors, are to perform an application programming interface (API) to indicate two or more groups of blocks of threads of a software kernel to be performed on a graphics processing unit (GPU), wherein the API is to indicate the two or more groups of blocks of threads by indicating one or more dimensions of the groups of blocks of threads.

29 . The non-transitory machine-readable medium of claim 28 , wherein the one or more processors are to further indicate that the two or more groups of blocks of threads are scheduled in parallel.

30 . The non-transitory machine-readable medium of claim 28 , wherein the one or more processors are to further indicate the two or more groups of blocks of threads by setting a

Assignees

• Nvidia Corp

Inventors

• Long Ze
• Perelygin Kyrylo
• Edwards Harold Carter
• Hirisave Chandra Shekhara Gokul Ramaswamy
• Marathe Jaydeep
• Krashinsky Ronny Meir
• Bharambe Girish Bhaskarrao

Classifications

• G06F9/505

  considering the load · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F8/456 Primary

  Parallelism detection · CPC title