Systems and methods for structured mixed-precision in a specialized processing block

Patent metadata

Field	Value
Publication number	US-12554464-B2
Application number	US-202117559338-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values having multiple precisions, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

First claim

What is claimed is:

1 . A digital signal processing (DSP) block comprising:
a plurality of weight registers configurable to receive and store a first plurality of values, wherein the first plurality of values comprises a first portion and a second portion, wherein:
the first portion comprises one or more first values of the first plurality of values having a first precision; and
the second portion comprises one or more second values of the first plurality of values having a second precision;
a plurality of multipliers, wherein each respective multiplier of the plurality of multipliers is configurable to receive a respective value of the first plurality of values, wherein the plurality of multipliers comprises:
one or more first multipliers configurable to perform multiplication involving values having the first precision; and
one or more second multipliers configurable to perform multiplication involving values having the second precision;
one or more inputs configurable to receive a second plurality of values; a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the plurality of multipliers, wherein the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products, wherein:
in a first mode of operation, the multiplexer network is configurable to route the second plurality of values to the one or more first multipliers and the one or more second multipliers; and
in a second mode of operation, the multiplexer network is configurable to route the second plurality of values only to the one or more first multipliers; and
adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

2 . The DSP block of claim 1 , comprising a plurality of control registers configurable to store a third plurality of values, wherein:
the multiplexer network is configurable to receive the third plurality of values from the plurality of control registers; and route the second plurality of values based on the third plurality of values.

3 . The DSP block of claim 2 , wherein the values of the third plurality of values are respectively indicative of whether a value of the second plurality of values is either to be multiplied by a value of the first portion of the first plurality of values or multiplied by a value of the second portion of the first plurality of values.

4 . The DSP block of claim 1 , wherein:
the first precision is more precise than the second precision; and the multiplexer network is configurable to:
route a first portion of the second plurality of values to the one or more first multipliers; and
route a second portion of the second plurality values to the one or more second multipliers;
the plurality of multipliers is configurable to generate the plurality of products by:
generating one or more first products by multiplying each of the one or more first values by a value of the first portion of the second plurality of values; and
generating one or more second products by multiplying each of the one or more second values by a value of the second portion of the second plurality of values.

5 . The DSP block of claim 4 , wherein the one or more second multipliers are not configurable to perform multiplication between values having the first precision.

6 . The DSP block of claim 4 , wherein the adder circuitry is configurable to:
generate the first sum by adding the one or more first products; and generate the second sum by adding the one or more second products.

7 . The DSP block of claim 6 , wherein the adder circuitry comprises:
a first adder configurable to generate a third sum by adding the first sum and the second sum; a second adder configurable to generate a fourth sum by adding the second sum and a first value received from a second DSP block; and a third adder configurable to generate a fifth sum by:
adding the first sum and a second value received from the second DSP block; or
adding the third sum and the second value received from the second DSP block.

8 . The DSP block of claim 1 , wherein:
the first precision and the second precision are of the same precision; and the plurality of multipliers is configurable to generate the plurality of products using only the one or more first multipliers.

9 . The DSP block of claim 1 , wherein the DSP block is part of a field programmable gate array (FPGA).

10 . An integrated circuit device comprising:
a digital signal processing (DSP) block, the DSP block comprising:
a plurality of weight registers configurable to receive and store a first plurality of values, wherein the first plurality of values comprises a first portion and a second portion, wherein:
the first portion comprises one or more first values of the first plurality of values having a first precision; and
the second portion comprises one or more second values of the first plurality of values having a second precision;

a plurality of multipliers, wherein each respective multiplier of the plurality of multipliers is configurable to receive a respective value of the first plurality of values, wherein the plurality of multipliers comprises:
one or more first multipliers configurable to perform multiplication involving values having the first precision; and
one or more second multipliers configurable to perform multiplication involving values having the second precision;

one or more inputs configurable to receive a second plurality of values;
a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the plurality of multipliers, wherein the plurality of multipliers is configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products, wherein:
in a first mode of operation, the multiplexer network is configurable to route the second plurality of values to the one or more first multipliers and the one or more second multipliers; and
in a second mode of operation, the multiplexer network is configurable to route the second plurality of values only to the one or more first multipliers; and

adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

11 . The integrated circuit device of claim 10 , comprising a plurality of control registers configurable to store a third plurality of values, wherein:
the values of the third plurality of values are respectively indicative of whether a value of the second plurality of values is either to be multiplied by a value of the first portion of the first plurality of values or multiplied by a value of the second portion of the first plurality of values; the multiplexer network is configurable to receive the third plurality of values from the plurality of control registers; and route the second plurality of values based on the third plurality of values.

12 . The integrated circuit device of claim 11 , wherein the multiplexer network comprises a plurality of multiplexers each configurable to:
receive at least two values of the second plurality of values; receive a respective value of the third plurality of values; and route one of the at least two values of the second plurality of values to a multiplier of the plurality of multipliers based on the respective value of the third plurality of values.

Assignees

• Langhammer Martin
• Wu Michael
• Tunali Nihat Engin
• Altera Corp

Inventors

• Langhammer Martin
• Wu Michael
• Tunali Nihat Engin

Classifications

• G06F7/50

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06N3/10

  Interfaces, programming languages or software development kits, e.g. for simulating neural networks · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title