Array substrate and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-12554168-B2
Application number	US-202218248957-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

An array substrate includes a substrate, a first gate line, a plurality of data lines, a plurality of first pixel electrodes, a plurality of first transistors and a plurality of first capacitive lines that are all disposed on the substrate. A data line and the first gate line cross, and are insulated from each other. An orthographic projection of a first capacitive line on the substrate is overlapped with an orthographic projection of a first pixel electrode on the substrate. The first capacitive line includes a first conductive segment that is proximate to the first gate line and is provided with a first break therein. An orthographic projection, on the substrate, of a portion of the first conductive segment located on a side of the first break away from the middle subsection is overlapped with an orthographic projection of a second electrode of a first transistor on the substrate.

First claim

What is claimed is:

1 . An array substrate comprising a substrate, and a first gate line, a plurality of data lines, a plurality of first pixel electrodes, a plurality of first transistors and a plurality of first capacitive lines that are all disposed on the substrate; wherein
the first gate line has a first side and a second side opposite to each other in a width direction of the first gate line; a data line and the first gate line cross, and are insulated from each other; a first pixel electrode is located on the first side of the first gate line; a gate, a first electrode and a second electrode of a first transistor are coupled to the first gate line, the data line and the first pixel electrode, respectively; an orthographic projection of a first capacitive line on the substrate is overlapped with an orthographic projection of the first pixel electrode on the substrate; the first capacitive line includes a first conductive segment whose extending direction is substantially parallel to an extending direction of the first gate line, and the first conductive segment is proximate to the first gate line; the first conductive segment is provided with a first break therein, and the first break is located on a side of a charging coupling point away from the data line, and deviates from a middle subsection of the first conductive segment; the charging coupling point is a coupling position of the first pixel electrode and the second electrode of the first transistor, and the middle subsection of the first conductive segment is a portion of the first conductive segment that is located in the middle and has a length of ⅓ of a total length of the first conductive segment; an orthographic projection, on the substrate, of a portion of the first conductive segment located on a side of the first break away from the middle subsection is overlapped with an orthographic projection of the second electrode of the first transistor on the substrate.

2 . The array substrate according to claim 1 , wherein the first break is located on a side of the middle subsection of the first conductive segment proximate to the charging coupling point.

3 . The array substrate according to claim 1 , wherein the orthographic projection, on the substrate, of the portion of the first conductive segment located on the side of the first break away from the middle subsection, the orthographic projection of the second electrode of the first transistor on the substrate, and the orthographic projection of the first pixel electrode on the substrate are overlapped with each other.

4 . The array substrate according to claim 1 , wherein the first conductive segment is provided with a recess whose opening faces the first gate line or faces away from the first gate line; the recess and the first break are respectively disposed on two sides of the middle subsection.

5 . The array substrate according to claim 4 , wherein an orthographic projection, on the substrate, of a portion of the first conductive segment located on a side of the recess away from the middle subsection is overlapped with the orthographic projection of the second electrode of the first transistor on the substrate.

6 . The array substrate according to claim 4 , wherein at the recess, a ratio of a width of a retained portion of the first conductive segment to a width of the first conductive segment is in a range of ⅓ to ½, inclusive; and/or a width of the opening of the recess is in a range of 7.5 μm to 8.5 μm, inclusive.

7 . The array substrate according to claim 1 , wherein the portion of the first conductive segment located on the side of the first break away from the middle subsection has a length of greater than or equal to 15 μm.

8 . The array substrate according to claim 1 , wherein the first gate line has a first gate line break;
the array substrate further comprises a first bridge, and two ends of the first bridge are respectively connected to two sides of the first gate line break in the first gate line; the first bridge and a first repair capacitive line cross, and the first repair capacitive line is one of the plurality of first capacitive lines; the first repair capacitive line has a first repair break and a second repair break respectively disposed on two sides of the first bridge, and the first repair break is located in a first conductive segment of the first repair capacitive line; wherein one of the first repair break and the second repair break is a first break in the first conductive segment of the first repair capacitive line, or the first repair break and the second repair break are respectively located on two sides of the first break in the first conductive segment of the first repair capacitive line; and a portion of the first conductive segment of the first repair capacitive line located on a side of the first repair break away from the first bridge is coupled to a second electrode of a first repair transistor; the first repair transistor is one of the plurality of first transistors, and corresponds to the first repair capacitive line.

9 . The array substrate according to claim 8 , wherein
the first repair capacitive line includes a recess located in the first conductive segment; and one of the first repair break and the second repair break is located at a position where the recess of the first repair capacitive line is located.

10 . The array substrate according to claim 8 , wherein
the first repair break is located between the first bridge and a charging coupling point of the first pixel electrode and the second electrode of the first repair transistor; and the second electrode of the first repair transistor, the first pixel electrode and the first repair capacitive line are coupled at the charging coupling point of the first pixel electrode and the second electrode of the first repair transistor.

11 . The array substrate according to claim 1 , wherein the first gate line has a second gate line break;
the array substrate further comprises a second bridge, and two ends of the second bridge are respectively connected to two sides of the second gate line break in the first gate line; the second bridge crosses a second repair capacitive line and a third repair capacitive line, and each of the second repair capacitive line and the third repair capacitive line is one of the plurality of first capacitive lines; the second repair capacitive line has a third repair break and a fourth repair break respectively disposed on two sides of the second bridge, and the third repair break is located in a first conductive segment of the second repair capacitive line; a portion of the first conductive segment of the second repair capacitive line located on a side of the third repair break away from a middle subsection of the first conductive segment of the second repair capacitive line is coupled to a second electrode of a second repair transistor; the second repair transistor is one of the plurality of first transistors, and corresponds to the second repair capacitive line; the third repair capacitive line has a fifth repair break and a sixth repair break respectively disposed on the two sides of the second bridge, and the fifth repair break is located in a first conductive segment of the third repair capacitive line; a portion of the first conductive segment of the third repair capacitive line located on a side of the fifth repair break away from a middle subsection of the first conductive segment of the third repair capacitive line is coupled to a second electrode of a third repair transistor; the third repair transistor is one of the plurality of first transistors, and corresponds to the third repair capacitive line; wherein the third repair break

Assignees

• Chengdu Boe Display Sci Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhao Yijing
• Xie Chao
• Yang Yudan
• Yang Xi
• Xiong Tao

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• G02F1/136263 Primary

  Line defects · CPC title