Selective stencil mask and a stencil printing method

Patent metadata

Field	Value
Publication number	US-12552192-B2
Application number	US-202418619148-A
Country	US
Kind code	B2
Filing date	Mar 27, 2024
Priority date	Mar 29, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A selective stencil mask and a stencil printing method are provided. The stencil mask is for printing a fluid material onto a substrate, and comprises: a stencil member comprising: at least one printing region each having an array of apertures that allow the fluid material to flow therethrough and deposit onto the substrate; and a blocking region configured to prevent the fluid material from flowing therethrough; and a supporting member attached to the stencil member and configured to, when the stencil mask is placed on the substrate, contact the substrate and create a gap between the stencil member and the substrate.

First claim

What is claimed is:

1 . A method for forming a semiconductor package, comprising:
providing a first substrate and a second substrate; forming in a first region of the first substrate a first plurality of solder bumps using a first stencil mask; forming in a second region of the first substrate a second plurality of solder bumps using a second stencil mask; forming solder bumps on the second substrate; aligning the first plurality of solder bumps and the second plurality of solder bumps on the first substrate with the solder bumps on the second substrate to connect the first substrate with the second substrate; and reflowing the first plurality of solder bumps and the second plurality of solder bumps on the first substrate and the solder bumps on the second substrate.

2 . The method of claim 1 , wherein the first region is at a central position of the first substrate, and the second region is at a peripheral position of the first substrate.

3 . The method of claim 1 , wherein the first plurality of solder bumps have a pitch that is smaller than that of the second plurality of solder bumps; and/or
wherein the first plurality of solder bumps have a size that is smaller than that of the second plurality of solder bumps.

4 . The method of claim 1 , wherein the second stencil mask comprises:
a stencil member comprising a printing region having an array of apertures that allow a solder material to flow therethrough and being aligned with the second region of the first substrate when the second stencil mask is placed on the first substrate; and a blocking region for preventing the solder material from flowing therethrough and being aligned with the first region of the first substrate when the second stencil mask is placed on the first substrate; and a supporting member attached to the stencil member and configured to, when the stencil mask is placed on the substrate, contact the first substrate and create a gap between the second stencil member and the first substrate.

5 . A method for forming a semiconductor package, comprising:
providing a first substrate and a second substrate; forming in a first region of the first substrate a first plurality of solder bumps and in a second region of the first substrate a second plurality of solder bumps using a first stencil mask; depositing onto the second plurality of solder bumps flux using a second stencil mask;
forming solder bumps on the second substrate;
aligning the first plurality of solder bumps and the second plurality of solder bumps on the first substrate with the solder bumps on the second substrate to connect the first substrate with the second substrate; and
reflowing the first plurality of solder bumps and the second plurality of solder bumps on the first substrate and the solder bumps on the second substrate.

6 . The method of claim 5 , wherein the first region is at a central position of the first substrate, and the second region is at a peripheral position of the first substrate.

7 . The method of claim 5 , wherein the first plurality of solder bumps have a pitch that is smaller than that of the second plurality of solder bumps.

8 . The method of claim 5 , wherein the first plurality of solder bumps have a size that is smaller than that of the second plurality of solder bumps.

9 . The method of claim 5 , wherein the second stencil mask comprises:
a stencil member comprising a printing region having an array of apertures that allow the flux to flow therethrough and being aligned with the second region of the first substrate when the second stencil mask is placed on the first substrate; and a blocking region for preventing the flux from flowing therethrough and being aligned with the first region of the first substrate when the second stencil mask is placed on the first substrate; and
a supporting member attached to the stencil member and configured to, when the stencil mask is placed on the substrate, contact the first substrate and create a gap between the second stencil member and the first substrate.

10 . The method of claim 5 , before aligning the first plurality of solder bumps and the second plurality of solder bumps on the first substrate with the solder bumps on the second substrate to connect the first substrate with the second substrate; the method further comprising:
forming flux on the solder bumps on the second substrate using a dipping process.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Park Hyunseok
• Koo Kyowang
• Kim Seongkuk
• Heo Seokbeom

Classifications

• H10W72/01923

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/01223

  in liquid form, e.g. by dispensing droplets or by screen printing · CPC title

• H10W72/01257

  by reflowing · CPC title