Method of attaching components to printed cirucuit board with reduced accumulated tolerances

Patent metadata

Field	Value
Publication number	US-9865479-B2
Application number	US-201615130202-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Apr 15, 2016
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.

First claim

What is claimed is:

1. A method of attaching components to plurality of pads on a printed circuit board (PCB), the pads being arranged in a predetermined pattern, the method comprising:
placing a first stencil over the PCB, the first stencil defining a plurality of first apertures corresponding to first pads of the plurality of pads on the PCB;
applying solder paste through the first apertures in the first stencil to provide corresponding solder paste deposits on the first pads;
reflowing the solder paste deposits to form corresponding solder bumps on the first pads, respectively;
placing a second stencil over the PCB, the second stencil defining a plurality of second apertures, the plurality of second apertures comprising a first group of second apertures corresponding to the first pads;
applying flux through the second apertures in the second stencil to provide flux deposits on the solder bumps;
placing at least one component on the flux deposits; and
reflowing the flux deposits and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.

2. The method of claim 1 , further comprising:
performing a coining process on the solder bumps formed on the first pads to provide flattened surfaces of the solder bumps, wherein the flattened surfaces of the solder bumps are substantially co-planar.

3. The method of claim 1 , further comprising:
performing a solder paste inspection of the solder paste deposits on the first pads before reflowing the solder paste.

4. The method of claim 1 , wherein the at least one component comprises a surface mount technology (SMT) component.

5. The method of claim 1 , wherein the at least one component comprises a flip chip component.

6. The method of claim 1 , further comprising:
cleaning flux residue from the PCB.

7. The method of claim 1 , wherein the plurality of second apertures further comprise a second group of second apertures defined in the second stencil corresponding to second pads of the plurality of pads on the PCB, the second pads having no corresponding first apertures defined in the first stencil,
wherein applying the flux through the second apertures in the second stencil further provides flux deposits on the second pads, and
wherein placing the at least one component on the flux deposits includes placing another component on the flux deposits on the second pads.

8. The method of claim 7 , wherein the other component comprises a flip chip component.

9. The method of claim 8 , wherein the flip chip component includes previously formed solder bumps configured to align with the second pads when placed on the flux deposits on the second pads, and
wherein reflowing the flux deposits and the solder bumps includes reflowing the solder bumps on the flip chip component, forming corresponding solder joints between the other component and the second pads.

10. The method of claim 1 , wherein applying the solder paste comprises spreading the solder paste over a top surface of the first stencil using a squeegee, and wherein applying the flux comprises spreading the flux over a top surface of the second stencil using a squeegee.

11. The method of claim 1 , wherein the solder paste comprises a mixture of solder and flux in predetermined proportions.

12. A method of attaching components to a plurality of pads on a printed circuit board (PCB), wherein total accumulated tolerances of the method are reduced by separating accumulated tolerances into multiple processes, the method comprising:
performing a first process having a first accumulated tolerance, the first process comprising:
placing a first stencil over the PCB, the first stencil defining a plurality of first apertures corresponding to the pads on the PCB;
printing solder paste onto the pads using the first stencil;
reflowing the printed solder paste to form corresponding solder bumps on the pads, respectively;

performing a second process having a second accumulated tolerance, the second process comprising:
placing a second stencil over the PCB, the second stencil defining a plurality of second apertures corresponding to the pads on the PCB;
printing flux onto the solder bumps using the second stencil;
placing at least one component on the printed flux; and
reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.

13. The method of claim 12 , wherein performing the first process further comprises:
performing a coining process on the solder bumps formed on the pads to provide flattened surfaces of the solder bumps.

14. The method of claim 12 , wherein performing the first process further comprises:
performing a solder paste inspection of the printed solder paste on the pads before reflowing the printed solder paste.

15. The method of claim 12 , wherein performing each of the first process and the second process further comprises:
cleaning residual flux from the PCB.

16. A method of attaching a component to at least one pad on a printed circuit board (PCB), the method comprising:
applying solder paste onto the at least one pad using a first stencil to provide at least one solder paste deposit on the at least one pad, respectively;
reflowing the at least one solder paste deposit to form a corresponding at least one solder bump on the at least one pad, respectively, before attaching the component to the at least one pad, providing a first accumulated tolerance;
applying flux onto the at least one solder bump using a second stencil to provide at least one flux deposit on the at least one solder bump, respectively;
placing the component on the at least one flux deposit; and
reflowing the at least one flux deposit and the at least one solder bump to form a corresponding a least one solder joint between the component and the at least one pad, respectively, providing a second accumulated tolerance,
wherein a combined first and second accumulated tolerances reduce total accumulated tolerance as compared to reflowing the at least one solder paste deposit after placing the component on the at least one solder paste deposit.

17. The method of claim 16 , wherein the component is placed on the at least one flux deposit without using low force component placement.

18. The method of claim 16 , wherein reflowing the at least one solder paste deposit to form the corresponding at least one solder bump on the at least one pad, respectively, before attaching the component to the at least one pad prevents solder paste squeeze-out and solder paste electrical shorts.

19. The method of claim 16 , wherein the first and second accumulated tolerances are determined using one of a root sum square and root mean square method.

20. The method of claim 16 , wherein the first and second accumulated tolerances are calculated as arithmetic sum tolerances, which provide worst-case maximum or minimum values.

Assignees

• Avago Technologies General Ip

Inventors

• Wang Wei-Shun
• Sun Li
• Alawani Ashish
• Lee Lea-Teng

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07234

  Using a reflow oven · CPC title

• H10W72/07227

  involving guiding structures, e.g. spacers or supporting members · CPC title