Carrier plate for preparing package substrate, package substrate structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12550774-B2
Application number	US-202318115043-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Mar 1, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A carrier plate for preparing a package substrate according to an embodiment includes a dielectric layer, a seed layer in the dielectric layer, and a copper pillar layer on the seed layer. A bottom end of the seed layer is higher than a lower surface of the dielectric layer. A top end of the copper pillar layer is lower than an upper surface of the dielectric layer. The upper and lower surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer.

First claim

What is claimed is:

1 . A carrier plate for preparing a package substrate, comprising:
a dielectric layer; a seed layer in the dielectric layer; and a copper pillar layer on the seed layer, wherein a bottom end of the seed layer is higher than a lower surface of the dielectric layer; a top end of the copper pillar layer is lower than an upper surface of the dielectric layer; and the lower and upper surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer arranged in a longitudinal direction; an upper surface of the first dielectric layer and a lower surface of the second dielectric layer are adhered; the seed layer and the copper pillar layer on the seed layer are provided in the second dielectric layer; a lower surface of the seed layer is flush with a lower surface of the second dielectric layer; the top end of the copper pillar layer is lower than an upper surface of the second dielectric layer; the first metal layer is provided on a lower surface of the first dielectric layer; and the second metal layer is provided on the upper surface of the second dielectric layer, wherein a first via hole exposing the seed layer is provided in the first dielectric layer, the first via hole penetrating through the first metal layer; and a second via hole exposing the top end of the copper pillar layer is provided in the second dielectric layer, the second via hole penetrating through the second metal layer.

2 . The carrier plate of claim 1 , wherein the first metal layer has a same or similar thicknesses with that of the second metal layer.

3 . A package substrate structure comprising:
a first dielectric layer and a second dielectric layer arranged along a longitudinal direction, wherein an upper surface of the first dielectric layer and a lower surface of the second dielectric layer dielectric layer are adhered; a seed layer, a copper pillar layer on the seed layer and a second conductive pillar layer on the copper pillar layer are provided in the second dielectric layer; the lower surface of the seed layer is flush with the lower surface of the second dielectric layer; a first conductive pillar layer is provided in the first dielectric layer, the first conductive pillar layer being in communication with the seed layer; a first line layer is provided on the lower surface of the first dielectric layer; a second line layer is provided on an upper surface of the second dielectric layer; and the first line layer and the second line layer are conductively connected by the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer, wherein the package substrate structure further comprises a third dielectric layer on the first line layer and a fourth dielectric layer on the second line layer, wherein a third conductive pillar layer is provided in the third dielectric layer; a third line layer is provided on a lower surface of the third dielectric layer; the first line layer and the third line layer are conductively connected by the third conductive pillar layer; a fourth conductive pillar layer is provided in the fourth dielectric layer; a fourth line layer is provided on an upper surface of the fourth dielectric layer; and the second line layer and the fourth line layer are conductively connected by the fourth conductive pillar layer.

4 . The package substrate structure according to claim 3 , wherein the first dielectric layer and the second dielectric layer are same or different.

5 . The package substrate structure according to claim 3 , wherein the copper pillar layer comprises at least one copper pillar.

6 . The package substrate structure according to claim 3 , wherein the conductive pillar layer comprises at least one conductive pillar.

7 . The package substrate structure according to claim 3 , further comprising a first solder mask layer outside the third line layer and a second solder mask layer outside the fourth line layer; and
a first solder mask opening window and a second solder mask opening window are provided in the first solder mask layer and the second solder mask layer, respectively.

8 . A manufacturing method for a package substrate structure, comprising the steps of:
(a) preparing a first dielectric layer, and respectively forming a first metal layer on upper and lower surfaces of the first dielectric layer; (b) preparing a copper pillar layer on the first metal layer on the upper surface of the first dielectric layer, and etching the first metal layer exposed on the upper surface of the first dielectric layer to form a seed layer; (c) forming a second dielectric layer on the copper pillar layer, adhering a lower surface of the second dielectric layer and an upper surface of the first dielectric layer, a top end of the copper pillar layer being lower than an upper surface of the second dielectric layer; (d) forming a second metal layer on the upper surface of the second dielectric layer; (e) forming a first via hole exposing the seed layer in the first dielectric layer, the first via hole penetrating through the first metal layer, forming a second via hole exposing the top end of the copper pillar layer in the second dielectric layer, the second via hole penetrating through the second metal layer, forming by the seed layer a bottom end of the copper pillar layer, and respectively exposing by the second via hole and the first via hole the top end and the bottom end of the copper pillar layer.

9 . The manufacturing method according to claim 8 , further comprising:
(f), after step (e), electroplating the first via hole to form a first conductive pillar layer, and electroplating the second via hole to form a second conductive pillar layer, wherein the first metal layer on the lower surface of the first dielectric layer and the second metal layer are conductively connected by the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

10 . The manufacturing method according to claim 9 , further comprising:
(g) after step (f), processing the first metal layer to form a first line layer, and processing the second metal layer to form a second line layer, wherein the first line layer and the second line layer are conductively connected by the first conductive pillar layer, the copper pillar layer and the second conductive pillar layer.

11 . The manufacturing method according to claim 10 , further comprising:
(h) after step (g), forming a third dielectric layer on the first line layer and a fourth dielectric layer on the second line layer; (i) forming a third metal layer on the third dielectric layer and a fourth metal layer on the fourth dielectric layer; (j) forming a third conductive pillar layer in the third dielectric layer, and forming a fourth conductive pillar layer in the fourth dielectric layer, wherein the first line layer and the third metal layer are conductively connected by the third conductive pillar layer, and the second line layer and the fourth metal layer are conductively connected by the fourth conductive pillar layer; (k) processing the third metal layer to form a third line layer, and processing the fourth metal layer to form a fourth line layer, wherein the first line layer and the third line layer are conductively connected by the third conductive pillar layer, and the second line layer and the fourth line layer are conductively connected by the fourth conductive pillar layer; (l) forming a first solder mask layer outside the third line layer, forming a second solder mask layer outside

Assignees

• Zhuhai Access Semiconductor Co Ltd

Inventors

• Chen Xianming
• Feng Jindong
• Huang Benxia
• Huang Gao
• Huang Juchen

Classifications

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title