Method of forming package structure

Patent metadata

Field	Value
Publication number	US-11817437-B2
Application number	US-202117516458-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Nov 28, 2016
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

First claim

What is claimed is:

1. A package structure comprising:
a first semiconductor package comprising a dielectric structure, a semiconductor device on the dielectric structure and an under bump metallization (UBM) structure in the dielectric structure, the UBM structure comprising a seed layer and a conductive feature thicker than the seed layer, wherein the seed layer is on a bottom surface of the conductive feature at a greatest distance from the semiconductor device, and the seed layer has an outermost sidewall aligned with an outermost sidewall of the conductive feature, and the outermost sidewall of the conductive feature is in contact with the dielectric structure;
a conductive bump below the UBM structure;
a second semiconductor package over the first semiconductor package;
an electrical connector electrically connecting the second semiconductor package to the first semiconductor package; and
an epoxy material encapsulating the electrical connector.

2. The package structure of claim 1 , wherein the first semiconductor package further comprises a redistribution line, the redistribution line has a linear portion extending in parallel with a bottom surface of the dielectric structure, and a protruding portion protruding from the linear portion to the UBM structure, wherein the protruding portion has a width decreasing in a first direction, and the UBM structure has a width decreasing in a second direction opposite the first direction.

3. The package structure of claim 1 , wherein the first semiconductor package further comprises a redistribution line over the UBM structure, the redistribution line comprises a seed layer and a conductive feature thicker than the seed layer, and the seed layer of the redistribution line is in contact with the conductive feature of the UBM structure.

4. The package structure of claim 1 , wherein the first semiconductor package further comprises a contact pad extending from a top surface of the dielectric structure into the dielectric structure, the contact pad has a width decreasing in a first direction, and the UBM structure has a width decreasing in a second direction opposite the first direction.

5. The package structure of claim 1 , wherein the first semiconductor package further comprises a contact pad having a top surface level with a top surface of the dielectric structure, the contact pad has a seed layer and a conductive feature extending upwards from the seed layer to the semiconductor device.

6. The package structure of claim 1 , wherein the first semiconductor package further comprises a molding compound encapsulating the semiconductor device, and a through via extending through the molding compound.

7. The package structure of claim 6 , wherein the through via comprises a seed layer and a conductive feature extending upwards from the seed layer to the electrical connector.

8. The package structure of claim 1 , wherein the epoxy material also encapsulates the second semiconductor package.

9. The package structure of claim 1 , wherein the epoxy material is in contact with a top surface of the first semiconductor package and a bottom surface of the second semiconductor package.

10. A package structure comprising:
a first semiconductor package comprising a dielectric structure, a semiconductor device over the dielectric structure, a molding compound encapsulating the semiconductor device, and an under bump metallization (UBM) structure in the dielectric structure;
a second semiconductor package over the first semiconductor package;
an underfill layer having a bottom surface in contact with a top surface of the semiconductor device, a top surface of the molding compound of the first semiconductor package and a bottom surface of the second semiconductor package;
an electrical connector electrically connecting the first and second semiconductor packages and encapsulated in the underfill layer; and
a conductive bump in contact with the UBM structure.

11. The package structure of claim 10 , wherein the underfill layer is also in contact with a top surface of the semiconductor device of the first semiconductor package.

12. The package structure of claim 10 , wherein the underfill layer has a bottom surface level with a bottom surface of the electrical connector.

13. The package structure of claim 10 , wherein the underfill layer has a topmost position level with a top surface of the second semiconductor package.

14. The package structure of claim 10 , wherein the electrical connector is a solder ball, a copper column, a copper stud, or a controlled collapse chip connector.

15. A package structure comprising:
a first semiconductor package comprising a dielectric structure, a semiconductor device on the dielectric structure, and a plurality of contact pads in the dielectric structure;
a second semiconductor package over the first semiconductor package, the second semiconductor package comprising one or more dies encapsulated in a first molding compound;
a resin material thermally coupling a top surface of the first semiconductor package to a bottom surface of the second semiconductor package, wherein a top position of the resin material is higher than a top position of the one or more dies, and the resin material is spaced apart from the one or more dies;
a conductive structure electrically coupling the second semiconductor package to the first semiconductor package, the conductive structure being in contact with the resin material; and
a plurality of bumps respectively in contact with the plurality of contact pads.

16. The package structure of claim 15 , wherein the resin material is in contact with the top surface of the first semiconductor package and the bottom surface of the second semiconductor package.

17. The package structure of claim 15 , wherein the resin material is in contact with an entirety of a sidewall of the conductive structure.

18. The package structure of claim 15 , wherein the first semiconductor package further comprises a plurality of redistribution lines between the plurality of contact pads and the semiconductor device, and the plurality of redistribution lines have protruding portions protruding toward the plurality of bumps.

19. The package structure of claim 18 , wherein the first semiconductor package further comprises a second molding compound encapsulating the semiconductor device, and a through via extending through the second molding compound to the conductive structure.

20. The package structure of claim 1 , wherein the epoxy material has a bottom surface in contact with a top surface of the semiconductor device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Tsai Po-Hao

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title