Substrate and method of manufacturing substrate

Patent metadata

Field	Value
Publication number	US-12550746-B2
Application number	US-202217857332-A
Country	US
Kind code	B2
Filing date	Jul 5, 2022
Priority date	Jul 12, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Provided is a method of manufacturing a substrate including an alignment mark, including: forming the alignment mark and a recess portion on the substrate, the alignment mark not penetrating the substrate and including a bottom portion with a lower infrared transmittance than that of a first surface and a second surface of the substrate; and aligning the substrate by orthogonally arranging predetermined positions of the first surface and the second surface of the substrate in a horizontal direction and an infrared ray camera and by image-identifying the alignment mark formed on the substrate with transmitted light of infrared rays emitted from the infrared ray camera.

First claim

What is claimed is:

1 . A method of manufacturing a substrate, comprising:
preparing a first silicon substrate including a first surface and a second surface, the second surface being a surface that is an opposite of the first surface; forming a resist layer on the first surface of the first silicon substrate; forming a pattern for processing an alignment mark and a pattern for processing a recess portion in the resist layer; forming, in the first silicon substrate, the alignment mark and the recess portion by concurrently dry etching the resist layer in which the pattern for processing the alignment mark and the pattern for processing the recess portion have been formed, the alignment mark not penetrating the first silicon substrate and including a bottom portion with a lower infrared transmittance than that of the first surface and the second surface; removing the resist layer from the first silicon substrate; preparing a second silicon substrate; and aligning the first silicon substrate and the second silicon substrate by disposing the second silicon substrate on a side facing the first surface of the first silicon substrate, by orthogonally arranging predetermined positions of the first surface and the second surface of the first silicon substrate in a horizontal direction and an infrared ray camera and by image-identifying the alignment mark formed on the first silicon substrate with transmitted light of infrared rays emitted from the infrared ray camera, wherein an opening width of the alignment mark is narrower than an opening width of the recess portion, and wherein, in the first silicon substrate, a first silicon layer, an oxidized layer, and a second silicon layer are laminated in an order from the first surface toward the second surface, and the recess portion is formed in such a way as to penetrate from the first surface toward the second surface of the first silicon substrate.

2 . The method according to claim 1 , wherein the predetermined positions are positions in which the alignment mark formed on the first silicon substrate can be image-identified by the transmitted light emitted from the infrared ray camera.

3 . The method according to claim 1 , wherein in the forming, the alignment mark is formed in a region of low plasma density in the first silicon substrate.

4 . The method according to claim 1 , wherein in the forming, the alignment mark is formed at a position close to the recess portion.

5 . The method according to claim 1 , wherein in the forming, a groove portion in a frame shape is formed to surround the alignment mark.

6 . The method according to claim 1 , wherein in the forming, the alignment mark is formed of a plurality of holes that do not penetrate the first silicon substrate.

7 . The method according to claim 6 , wherein in an aggregate of the plurality of holes, an aggregate portion including nearest adjacent holes is a mark aggregate, a hole on an outermost side in the mark aggregate is an outermost side hole, and a side arranged on the outermost side of the mark aggregate in the outermost side hole is an outermost side-side, and
wherein a closed curve including the mark aggregate and also including a plurality of outermost side-sides is aligned as a part of an identification shape of the alignment mark.

8 . The method according to claim 6 , wherein in an aggregate of the plurality of holes, an aggregate portion including the nearest adjacent holes is a mark aggregate, and for the mark aggregate, an alignment mark observation optical system is set such that image contrast corresponding to a portion between adjacent holes in an optical image of the alignment mark is out of a range of the alignment mark and is also darker than a background portion including no structure.

9 . The method according to claim 1 , further comprising:
after the aligning, bonding together the first silicon substrate and the second silicon substrate.

10 . The method according to claim 1 , wherein the dry etching is a Bosch process using reactive etching.

11 . The method according to claim 1 , wherein a plurality of recess portions, each being the recess portion, are provided in the first silicon substrate.

12 . The method according to claim 1 , wherein the bottom portion of the alignment mark includes a curved surface.

13 . The method according to claim 12 , wherein when an opening width of the alignment mark is defined as a chord length, the curved surface has a sagitta that is six percent or more of the chord length.

Assignees

• Canon Kk
• Canon Kabishiki Kaisha

Inventors

• Toshishige Mitsunori
• Fukumoto Yoshiyuki

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/201

  located on the periphery of wafers, e.g. orientation notches or lot numbers · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L2223/54426

  Electricity · mapped topic

• H01L23/544 Primary

  Electricity · mapped topic