Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12550676-B2
Application number	US-202318305606-A
Country	US
Kind code	B2
Filing date	Apr 24, 2023
Priority date	Jun 17, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A method of manufacturing a semiconductor device having first and second main surfaces opposite to each other. The method includes: forming a first electrode at the first main surface of the semiconductor wafer; applying a first tape to the second main surface of the semiconductor wafer; forming roughness at a portion of a surface of the first tape; applying a second tape to an outer peripheral portion of the semiconductor wafer, so as to cover the portion of the surface of the first tape, with the roughness formed thereon, at the second main surface of the semiconductor wafer, to cover a portion of the first main surface of the semiconductor wafer, and to cover a side surface of the semiconductor wafer; heating the semiconductor wafer after the first and second tapes are applied; and subsequently forming a plated film at the surface of the first electrode by a plating treatment.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device having a first main surface and a second main surface that is opposite to the first main surface, the method comprising:
as a first process, forming a first electrode at the first main surface of the semiconductor wafer; as a second process, applying a first tape to cover the second main surface of the semiconductor wafer; as a third process, forming roughness at a portion of a surface of the first tape; as a fourth process, applying a second tape to an outer peripheral portion of the semiconductor wafer, so as to cover the portion of the surface of the first tape, at which the roughness is formed in the third process, at the second main surface of the semiconductor wafer, to cover a portion of the first main surface of the semiconductor wafer, and to cover a side surface of the semiconductor wafer; as a fifth process, heating the semiconductor wafer after the first tape and the second tape are applied; and as a sixth process, forming a plated film at the surface of the first electrode by a plating treatment after the fifth process.

2 . The method, according to claim 1 , wherein
in the third process, forming the roughness includes pressing a mold against the portion of the surface of the first tape.

3 . The method according to claim 1 , wherein in the third process,
the first tape includes a base material layer, and a height difference of the portion of the surface of the first tape, after the roughness is formed, is less than a thickness of the base material layer.

4 . The method according to claim 3 , wherein
the height difference is not more than 10 μm.

5 . The method according to claim 1 , wherein
the semiconductor wafer further has a center portion, a thickness of the center portion being smaller than a thickness of the outer peripheral portion, thereby forming a rib-like shape, and in the third process, the roughness is formed at a portion of the first tape covering the outer peripheral portion of the semiconductor wafer.

Assignees

• Fuji Electric Co Ltd

Inventors

• Hashimoto Kohichi
• Tanaka Shunsuke
• Takahashi Yuya

Classifications

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10D12/441

  Vertical IGBTs · CPC title

• H10P72/7402 Primary

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title