Display panel and display apparatus

US12550546B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12550546-B2
Application numberUS-202017759701-A
CountryUS
Kind codeB2
Filing dateMar 18, 2020
Priority dateMar 18, 2020
Publication dateFeb 10, 2026
Grant dateFeb 10, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are a display panel and a display apparatus. The display panel includes: a base substrate including a notch area, a display area and a first non-display area between the notch area and the display area; a first conductive layer on the base substrate; a target insulating layer between the first conductive layer and the base substrate; and a functional layer between the target insulating layer and the base substrate. The display area includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a connecting through hole, wherein the connecting through hole runs through the target insulating layer, and the first conductive layer is electrically connected to the functional layer by the connecting through hole. The first non-display area includes at least one auxiliary through hole which runs through the target insulating layer and is not filled with a conductive material.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A display panel, comprising: a base substrate, comprising a notch area, a display area and a first non-display area, wherein the first non-display area is located between the notch area and the display area; a first conductive layer, disposed on the base substrate; a target insulating layer, disposed between the first conductive layer and the base substrate; and a functional layer, disposed between the target insulating layer and the base substrate; wherein in the display area, a plurality of sub-pixels, a plurality of data lines, a plurality of scanning lines and a plurality of light-emitting control lines are provided, wherein at least one of the plurality of sub-pixels comprises a connecting through hole, the connecting through hole runs through the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connecting through hole; in the first non-display area, at least one auxiliary through hole, a plurality of data transmission lines, a plurality of scanning transmission lines and a plurality of light-emitting transmission lines are provided, wherein at least one of the plurality of data lines is electrically connected to at least one of the plurality of data transmission lines, at least one of the plurality of scanning lines is electrically connected to at least one of the plurality of scanning transmission lines, and at least one of the plurality of light-emitting control lines is electrically connected to at least one of the plurality of light-emitting transmission lines; and in the first non-display area, an auxiliary region is formed by rounding of at least two types of transmission lines among the plurality of data transmission lines, the plurality of scanning transmission lines and the plurality of light-emitting transmission lines, and the auxiliary through hole is located in the auxiliary region, runs through the target insulating layer and is not filled with a conductive material; wherein the display panel further comprises: a first gate insulating layer, disposed between the semiconductor layer and the first conductive layer; a third conductive layer, disposed between the first gate insulating layer and the first conductive layer; a second gate insulating layer, disposed between the third conductive layer and the first conductive layer; a fourth conductive layer, disposed between the second gate insulating layer and the first conductive layer; and an interlayer dielectric layer, disposed between the fourth conductive layer and the first conductive layer; wherein at least one of the plurality of sub-pixels comprises: a first connecting through hole, a second connecting through hole and a third connecting through hole; wherein the first connecting through hole runs through the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; the second connecting through hole runs through the second gate insulating layer and the interlayer dielectric layer; and the third connecting through hole runs through the interlayer dielectric layer; the first conductive layer is electrically connected to the semiconductor layer through the first connecting through hole; the first conductive layer is electrically connected to the third conductive layer through the second connecting through hole; the first conductive layer is electrically connected to the fourth conductive layer through the third connecting through hole; and the auxiliary through hole is filled with an insulating material. 2 . The display panel according to claim 1 , further comprising: an interlayer insulating layer, disposed on a side of the first conductive layer facing away from the base substrate, wherein the auxiliary through hole is filled with a material of the interlayer insulating layer. 3 . The display panel according to claim 2 , wherein the functional layer comprises the semiconductor layer; the target insulating layer comprises: the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; the connecting through hole comprises the first connecting through hole; and the auxiliary through hole comprises a first auxiliary through hole, wherein the first auxiliary through hole runs through the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer, and a material filling the first auxiliary through hole runs through the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; wherein a distribution density of the first auxiliary through hole is smaller than or approximately equal to a distribution density of the first connecting through hole; or wherein an orthographic projection of the first auxiliary through hole on the base substrate does not overlap with orthographic projections of the semiconductor layer, the third conductive layer, the fourth conductive layer and the first conductive layer on the base substrate. 4 . The display panel according to claim 2 , wherein the functional layer comprises the third conductive layer; the target insulating layer comprises: the second gate insulating layer and the interlayer dielectric layer; the connecting through hole comprises the second connecting through hole; and the auxiliary through hole comprises a second auxiliary through hole, wherein the second auxiliary through hole runs through the second gate insulating layer and the interlayer dielectric layer, and a material filling in the second auxiliary through hole runs through the second gate insulating layer and the interlayer dielectric layer; wherein a distribution density of the second auxiliary through hole is smaller than or approximately equal to a distribution density of the second connecting through hole; or wherein an orthographic projection of the second auxiliary through hole on the base substrate does not overlap with the orthographic projections of the third conductive layer, the fourth conductive layer and the first conductive layer on the base substrate. 5 . The display panel according to claim 2 , wherein the functional layer comprises the fourth conductive layer; the target insulating layer comprises: the interlayer dielectric layer; the connecting through hole comprises the third connecting through hole; and the auxiliary through hole comprises a third auxiliary through hole, wherein the third auxiliary through hole runs through the interlayer dielectric layer, and a material filling the third auxiliary through hole runs through the interlayer dielectric layer; wherein a distribution density of the third auxiliary through hole is smaller than or approximately equal to a distribution density of the third connecting through hole; or wherein an orthographic projection of the third auxiliary through hole on the base substrate does not overlap with the orthographic projections of the fourth conductive layer and the first conductive layer on the base substrate. 6 . The display panel according to claim 1 , wherein the plurality of data transmission lines comprise a plurality of first data transmission lines; the first conductive layer comprises the plurality of data lines and the plurality of first data transmission lines; and the interlayer insulating layer has a plurality of first data through holes; and the display panel further comprises: a second conductive layer, disposed on a side of the interlayer insulating layer facing away from the base substrate and comprising a plurality of first data connecting portions; wherein at least one of the plurality of first data connecting portions is electrically connected to at least one of the plurality of data lines and at least one of the plurality of first data tr

Assignees

Inventors

Classifications

  • Interconnections, e.g. scanning lines · CPC title

  • characterised by the compositions or shapes of the interlayer dielectrics · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • characterised by materials, geometry or structure of the substrates · CPC title

  • Layout of electrodes and connections · CPC title

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Frequently asked questions

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What does patent US12550546B2 cover?
Disclosed are a display panel and a display apparatus. The display panel includes: a base substrate including a notch area, a display area and a first non-display area between the notch area and the display area; a first conductive layer on the base substrate; a target insulating layer between the first conductive layer and the base substrate; and a functional layer between the target insulatin…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).