Treatment to Control Deposition Rate

Patent metadata

Field	Value
Publication number	US-2018337040-A1
Application number	US-201816051064-A
Country	US
Kind code	A1
Filing date	Jul 31, 2018
Priority date	Nov 16, 2015
Publication date	Nov 22, 2018
Grant date	—

Abstract

A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
forming a spacer over a substrate, wherein the substrate comprises a first material that has a first atomic layer deposition growth rate and wherein the spacer comprises a second material with a second atomic layer deposition growth rate different from the first atomic layer deposition growth rate; adjusting the first atomic layer deposition growth rate to a third atomic layer deposition growth rate; and depositing a dielectric layer after the adjusting the first atomic layer deposition growth rate.

2 . The method of claim 1 , wherein the third atomic layer deposition growth rate is larger than the first atomic layer deposition growth rate.

3 . The method of claim 1 , wherein the third atomic layer deposition growth rate is smaller than the first atomic layer deposition growth rate.

4 . The method of claim 1 , wherein the adjusting the first atomic layer deposition growth rate further comprises introducing oxygen.

5 . The method of claim 1 , wherein the adjusting the first atomic layer deposition growth rate further comprises introducing F 2 .

6 . The method of claim 1 , wherein the depositing the dielectric layer forms a larger thickness over the substrate than over the spacer.

7 . The method of claim 1 , wherein the depositing the dielectric layer forms a larger thickness over the spacer than over the substrate.

8 . A method of manufacturing a semiconductor device, the method comprising:
forming a spacer over a substrate, the spacer comprising first terminal groups and the substrate comprising second terminal groups different from the first terminal groups; modifying the second terminal groups, wherein after the modifying the second terminal groups the first terminal groups remain; and growing a dielectric layer over both the substrate and the spacer after the modifying the second terminal groups, wherein after the growing the dielectric layer the dielectric layer has a larger thickness adjacent to the substrate than adjacent to the spacer.

9 . The method of claim 8 , wherein the modifying the second terminal groups comprises exposing the second terminal groups to oxygen.

10 . The method of claim 8 , wherein the first terminal groups comprise nitrogen.

11 . The method of claim 10 , wherein the second terminal groups comprise hydrogen.

12 . The method of claim 11 , wherein the modifying the second terminal groups replaces the hydrogen with oxygen.

13 . The method of claim 8 , wherein the dielectric layer has a thickness adjacent to the substrate of between about 43 and about 57 .

14 . The method of claim 8 , wherein the dielectric layer has a thickness adjacent to the spacer of between about 48 and about 52 .

15 . A method of manufacturing a semiconductor device, the method comprising:
forming a spacer adjacent to a gate stack over a semiconductor substrate, the spacer having first terminal groups with a first bond dissociation energy, the semiconductor substrate having second terminal groups with a second bond dissociation energy less than the first bond dissociation energy; changing the second terminal groups to third terminal groups, the third terminal groups having a third bond dissociation energy greater than the first bond dissociation energy; and reacting a first precursor with both the first terminal groups and the third terminal groups to deposit a dielectric layer.

16 . The method of claim 15 , wherein the first bond dissociation energy is 298 kJ/mol.

17 . The method of claim 16 , wherein the second bond dissociation energy is 439 kJ/mol.

18 . The method of claim 17 , wherein the third bond dissociation energy is 798 kJ/mol.

19 . The method of claim 15 , wherein the dielectric layer has a first thickness adjacent to the semiconductor substrate that is larger than a second thickness adjacent to the spacer.

20 . The method of claim 15 , wherein the changing the second terminal groups to the third terminal groups comprises replacing hydrogen atoms with oxygen atoms.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kao Wan-Yi
• Hsu Kuang-Yuan

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/69433 Primary

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6512 Primary

  by exposure to a gas or vapour · CPC title