Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12550339-B2
Application number	US-202318338021-A
Country	US
Kind code	B2
Filing date	Jun 20, 2023
Priority date	Sep 7, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor memory device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a memory structure including a first semiconductor layer opposed to the first conductive layers, a first wiring, a second conductive layer, a first insulating layer separating the plurality of first conductive layers in a second direction, a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate, and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate. The memory structure has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate; a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate; a memory structure extending in the first direction, the memory structure including a first semiconductor layer opposed to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers; a first wiring connected to an end portion on a side close to the substrate of the first semiconductor layer, the first wiring extending in a second direction intersecting with the first direction; a second conductive layer connected to an end portion on a side far from the substrate of the first semiconductor layer; a first insulating layer separating the plurality of first conductive layers in the second direction, the first insulating layer extending in a third direction and the first direction, the third direction intersecting with the first direction and the second direction; a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate among the plurality of first conductive layers in the second direction, the second insulating layer extending in the first direction and the third direction; and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate among the plurality of first conductive layers in the second direction, the third insulating layer extending in the first direction and the third direction, wherein the memory structure has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.

2 . The semiconductor memory device according to claim 1 , wherein
an end portion on the side far from the substrate of the memory structure includes an exposed portion in which a part of the gate insulating layer on a side surface is removed and a side surface of the first semiconductor layer is exposed, and the exposed portion is electrically connected to the second conductive layer.

3 . The semiconductor memory device according to claim 1 , comprising
a third conductive layer disposed along the first insulating layer, extending in the first direction and the third direction, and having one end connected to the second conductive layer.

4 . The semiconductor memory device according to claim 1 , wherein
a number of the second insulating layers disposed between the first insulating layers is larger than a number of the third insulating layers disposed between the first insulating layers.

5 . The semiconductor memory device according to claim 4 , wherein
the number of the third insulating layers disposed between the first insulating layers is one.

6 . The semiconductor memory device according to claim 1 , wherein
a number of the second insulating layers disposed between the first insulating layers is equal to a number of the third insulating layers disposed between the first insulating layers.

7 . The semiconductor memory device according to claim 1 , wherein
a width in the second direction of an end portion on a substrate side of the memory structure is larger than a width in the second direction of an end portion on an opposite side of the substrate of the memory structure, and a width in the second direction of an end portion on the substrate side of the third insulating layer is smaller than a width in the second direction of an end portion on an opposite side of the substrate of the third insulating layer.

8 . The semiconductor memory device according to claim 1 , wherein
the third insulating layer includes a first part that is positioned in a substrate side and separates the first conductive layer, and a second part that separates the second conductive layer, and the second part has a taper larger than a taper of the first part.

9 . The semiconductor memory device according to claim 1 , wherein
the second conductive layer is separated in the second direction by a fourth insulating layer, and the third insulating layer separates the fourth insulating layer and the first conductive layer in the second direction.

10 . A semiconductor memory device comprising:
a substrate; a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate; a memory structure extending in the first direction, the memory structure including a first semiconductor layer opposed to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers; a first wiring connected to an end portion on a side close to the substrate of the first semiconductor layer, the first wiring extending in a second direction intersecting with the first direction; a second conductive layer connected to an end portion on a side far from the substrate of the first semiconductor layer; a first insulating layer separating the plurality of first conductive layers in the second direction, the first insulating layer extending in a third direction and the first direction, the third direction intersecting with the first direction and the second direction; a second insulating layer separating one or a plurality of the first conductive layers disposed on a side closest to the substrate among the plurality of first conductive layers in the second direction, the second insulating layer extending in the first direction and the third direction; and a third insulating layer separating one or a plurality of the first conductive layers disposed on a side farthest from the substrate among the plurality of first conductive layers in the second direction, the third insulating layer extending in the first direction and the third direction, wherein the second insulating layer has a tapered shape having a width in the second direction decreasing with increasing distance from the substrate, and the third insulating layer has a tapered shape having a width in the second direction decreasing with decreasing distance from the substrate.

11 . The semiconductor memory device according to claim 10 , wherein
an end portion on the side far from the substrate of the memory structure includes an exposed portion in which a part of the gate insulating layer on a side surface is removed and a side surface of the first semiconductor layer is exposed, and the exposed portion is electrically connected to the second conductive layer.

12 . The semiconductor memory device according to claim 10 , comprising
a third conductive layer disposed along the first insulating layer, extending in the first direction and the third direction, and having one end connected to the second conductive layer.

13 . The semiconductor memory device according to claim 10 , wherein
a number of the second insulating layers disposed between the first insulating layers is larger than a number of the third insulating layers disposed between the first insulating layers.

14 . The semiconductor memory device according to claim 13 , wherein
the number of the third insulating layers disposed between the first insulating layers is one.

15 . The semiconductor memory device according to claim 10 , wherein
a number of the second insulating layers disposed between the first insulating layers is equal to a number of the

Assignees

• Kioxia Corp

Inventors

• Nakajima Yasuhito
• Noda Kosei

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title