Slicers and temperature offset cancelation circuits for decision feedback equalizers

Patent metadata

Field	Value
Publication number	US-12549417-B2
Application number	US-202418647959-A
Country	US
Kind code	B2
Filing date	Apr 26, 2024
Priority date	Apr 26, 2024
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A slicer of a decision feedback equalizer (DFE) comprises an integrator circuit, a regenerator circuit coupled to the integrator circuit, and a temperature offset cancelation circuit coupled to the regenerator circuit. The integrator circuit comprises a first transistor associated with a first temperature-dependent beta value. The temperature offset cancelation circuit comprises a second transistor associated with a second temperature dependent beta value, a pair of first and second resistors, and a third transistor coupled to the pair of first and second resistors. The first resistor is coupled to the second transistor. The pair of first and second resistors is to modify the second temperature-dependent beta value to correspond to the first temperature-dependent beta value of the first transistor. The third transistor is to provide a bias current for biasing the first transistor.

First claim

What is claimed is:

1 . A slicer of a decision feedback equalizer (DFE), the slicer comprising:
an integrator circuit comprising a first transistor associated with a first temperature-dependent beta value; a regenerator circuit coupled to the integrator circuit; a temperature offset cancelation circuit coupled to the regenerator circuit wherein the temperature offset cancelation circuit comprises:
a second transistor associated with a second temperature-dependent beta value;
a pair of first and second resistors, wherein the first resistor is coupled to the second transistor, and wherein the pair of first and second resistors is to modify the second temperature-dependent beta value to correspond to the first temperature-dependent beta value of the first transistor; and
a third transistor coupled to the pair of first and second resistors, the third transistor to provide a bias current for canceling a temperature offset of the first transistor.

2 . The slicer of claim 1 , wherein:
a source terminal of the second transistor is coupled to a source terminal of the third transistor and the second resistor; a gate terminal of the second transistor is coupled to a drain terminal of the second transistor and the first resistor; and a gate terminal of the third transistor is coupled to the first resistor, the second resistor, and an input current source.

3 . The slicer of claim 2 , wherein the input current source is a programmable current source.

4 . The slicer of claim 1 , wherein:
the first transistor is associated with a fourth transistor in a differential pair; and the fourth transistor is associated with a second temperature offset cancelation circuit corresponding to the temperature offset cancelation circuit.

5 . The slicer of claim 1 , wherein the first transistor, the second transistor, and the third transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

6 . The slicer of claim 1 , wherein the modification of the second temperature-dependent beta value is approximated by a product of the second temperature-dependent beta value and a quotient of a sum of the first and second resistors and the second resistor.

7 . The slicer of claim 1 , wherein:
the first transistor corresponds to fourth, fifth, and sixth transistors of respective second, third, and fourth slicers; a summer of the DFE is coupled to each of the slicer and the second, third, and fourth slicers via the first, fourth, fifth, and sixth transistors; and the first, fourth, fifth, and sixth transistors are to load the summer less than a threshold loading value.

8 . The slicer of claim 1 , wherein:
the temperature offset cancelation circuit is coupled to a fourth transistor of the regenerator circuit; the fourth transistor of the regenerator circuit is coupled to the first transistor of the integrator circuit; and the fourth transistor isolates the regenerator circuit from the integrator circuit.

9 . A temperature offset cancelation circuit comprising:
a first transistor associated with a first temperature-dependent beta value; a pair of first and second resistors, wherein the first resistor is coupled to the first transistor, and wherein the pair of first and second resistors is to modify the first temperature-dependent beta value to correspond to a second temperature-dependent beta value; and a second transistor coupled to the pair of first and second resistors, the second transistor to provide a bias current.

10 . The temperature offset cancelation circuit of claim 9 , wherein:
a source terminal of the first transistor is coupled to a source terminal of the second transistor and the second resistor; a gate terminal of the first transistor is coupled to a drain terminal of the first transistor and the first resistor; and a gate terminal of the second transistor is coupled to the first resistor, the second resistor, and an input current source.

11 . The temperature offset cancelation circuit of claim 10 , wherein the input current source is a programmable current source.

12 . The temperature offset cancelation circuit of claim 9 , wherein the first transistor and the second transistor are n-type metal-oxide-semiconductor (NMOS) transistors.

13 . The temperature offset cancelation circuit of claim 9 , wherein the modification of the first temperature-dependent beta value is approximated by a product of the first temperature-dependent beta value and a quotient of a sum of the first and second resistors and the second resistor.

14 . A Universal Serial Bus (USB) Physical Layer (PHY) of a USB system, the USB PHY comprising:
a decision feedback equalizer (DFE) comprising:
a summer; and
a slicer, the slicer comprising:
an integrator circuit comprising a first transistor, wherein the first transistor is associated with a first temperature-dependent beta value;
a regenerator circuit coupled to the integrator circuit;
a temperature offset cancelation circuit coupled to the regenerator circuit, wherein the temperature offset cancelation circuit comprises:
a second transistor associated with a second temperature-dependent beta value;
a pair of first and second resistors, wherein the first resistor is coupled to the second transistor, and wherein the pair of the first and second resistors is to modify the second temperature-dependent beta value to correspond to the first temperature-dependent beta value of the first transistor; and
a third transistor coupled to the pair of first and second resistors, the third transistor to provide a bias current for canceling a temperature offset of the first transistor.

15 . The USB PHY of claim 14 , wherein:
a source terminal of the second transistor is coupled to a source terminal of the third transistor and the second resistor; a gate terminal of the second transistor is coupled to a drain terminal of the second transistor and the first resistor; and a gate terminal of the third transistor is coupled to the first resistor, the second resistor, and an input current source.

16 . The USB PHY of claim 15 , wherein the input current source is a programmable current source.

17 . The USB PHY of claim 14 , wherein:
the first transistor is associated with a fourth transistor in a differential pair; and the fourth transistor is associated with a second temperature offset cancelation circuit corresponding to the temperature offset cancelation circuit.

18 . The USB PHY of claim 14 , wherein the modification of the second temperature-dependent beta value is approximated by a product of the second temperature-dependent beta value and a quotient of a sum of the first and second resistors and the second resistor.

19 . The USB PHY of claim 14 , wherein:
the first transistor corresponds to fourth, fifth, and sixth transistors of respective second, third, and fourth slicers; the summer is coupled to each of the slicer and the second, third, and fourth slicers via the first, fourth, fifth, and sixth transistors; and the first, fourth, fifth, and sixth transistors are to load the summer less than a threshold loading value.

20 . The USB PHY of claim 14 , wherein:
the temperature offset cancelation circuit is coupled to a fourth transistor of the regenerator circuit; the fourth transistor of the regenerator circuit is coupled to the first transistor of the integrator circuit; and the fourth transistor isolates the regenerator circuit from the integrator circuit.

Assignees

• Cypress Semiconductor Corp
• Infineon Technologies Americas Corp

Inventors

• Bodnaruk Nicholas
• Jung Soon-Gil
• Miller Gary
• Sunkara Sai Goutham
• Sanders Anthony

Classifications

• H04L25/03885 Primary

  adaptive · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/0349

  as a feedback filter · CPC title

• H04L25/03267 Primary

  with decision feedback equalisers · CPC title