Data transmission using delayed timing signals

Patent metadata

Field	Value
Publication number	US-12549168-B2
Application number	US-202418638218-A
Country	US
Kind code	B2
Filing date	Apr 17, 2024
Priority date	Nov 1, 2011
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

First claim

What is claimed is:

1 . A memory controller to control an operation of a memory device having a plurality of memory cells, the memory controller comprising:
a first interface circuit configured to receive a data signal including data accessed from the plurality of memory cells of the memory device; a second interface circuit configured to receive a first timing signal from the memory device, the first timing signal to time reception of the data signal; a first circuit configured to receive the first timing signal and delay the first timing signal by at least a first delay to produce a second timing signal, the first circuit including a logic gate that receives the second timing signal and is serially connected to one or more buffer circuits to generate a delayed first timing signal; a data circuit configured to capture the data from the data signal in response to the delayed first timing signal; a second circuit configured to delay the data signal to generate a delayed data signal; and a control circuit configured to control the first delay of the first circuit based on a phase comparison between the delayed data signal and the delayed first timing signal.

2 . The memory controller of claim 1 , wherein the first circuit further comprises:
a delay circuit configured to receive the first timing signal and delay the first timing signal by the first delay to generate the second timing signal, wherein the control circuit controls the first delay of the delay circuit based on the phase comparison.

3 . The memory controller of claim 2 , wherein the first circuit further comprises:
a multiplexor configured to receive the second timing signal from the delay circuit and output a third timing signal in response to a control signal, wherein the third timing signal and the control signal are input to the logic gate and wherein the logic gate is configured to output a fourth timing signal to the one or more buffer circuits according to a logical operation applied by the logic gate to the third timing signal and the control signal, wherein the one or more buffer circuits buffer the fourth timing signal to output the delayed first timing signal.

4 . The memory controller of claim 3 , wherein the control signal has constant logic high state.

5 . The memory controller of claim 3 , wherein the logic gate is an AND logic gate circuit.

6 . The memory controller of claim 1 , further comprising:
a phase comparator circuit configured to compare the delayed first timing signal with the delayed data signal to generate a phase comparison signal, the control circuit configured to control the first delay based on the phase comparison signal.

7 . The memory controller of claim 1 , wherein the second circuit comprises:
a replica circuit configured to delay the data signal during a replica mode of the memory controller to generate the delayed data signal, wherein the replica circuit is bypassed during a normal mode of the memory controller.

8 . The memory controller of claim 1 , wherein the delay of the second circuit is non-adjustable.

9 . A method of operation of a memory controller to control a memory device having a plurality of memory cells, the method comprising:
receiving, by a first interface circuit of the memory controller, a data signal including data accessed from the plurality of memory cells of the memory device; receiving, by a second interface circuit of the memory controller, a first timing signal from the memory device, the first timing signal to time reception of the data signal; delaying, by a first circuit of the memory controller, the first timing signal by at least a first delay to produce a second timing signal, and generating a delayed first timing signal using a logic gate that receives the second timing signal and is serially connected to one or more buffer circuits; capturing, by a data circuit of the memory controller, the data from the data signal in response to the delayed first timing signal; delaying, by a second circuit of the memory controller, the data signal to generate a delayed data signal; and controlling, by a control circuit of the memory controller, the first delay based on a phase comparison between the delayed data signal and the delayed first timing signal.

10 . The method of claim 9 , further comprising:
delaying, by a delay circuit of the memory controller, the first timing signal by the first delay to generate the second timing signal, wherein the first delay of the delay circuit is controlled by the control circuit based on the phase comparison to generate the second timing signal.

11 . The method of claim 10 , further comprising:
receiving, by a multiplexor included in the first circuit, the second timing signal from the delay circuit and outputting a third timing signal in response to a control signal, wherein the third timing signal and the control signal are input to the logic gate and a fourth timing signal is output by the logic gate to the one or more buffer circuits according to a logical operation applied by the logic gate to the third timing signal and the control signal, wherein the delayed first timing signal is output by buffering the fourth timing signal using the one or more buffer circuits.

12 . The method of claim 11 , wherein the control signal has constant logic high state.

13 . The method of claim 11 , wherein the logic gate is an AND logic gate circuit that outputs the fourth timing signal.

14 . The method of claim 9 , further comprising:
comparing, by a phase comparator, the delayed first timing signal with the delayed data signal to generate a phase comparison signal, wherein the first delay is controlled based on the phase comparison signal.

15 . The method of claim 9 , further comprising:
delaying, by a replica circuit, the data signal during a replica mode of the memory controller to generate the delayed data signal, and bypassing the replica circuit during a normal mode of the memory controller.

16 . A memory controller to control an operation of a memory device having a plurality of memory cells, the memory controller comprising:
a means for receiving a data signal including data accessed from the plurality of memory cells of the memory device; a means for receiving a first timing signal from the memory device, the first timing signal to time reception of the data signal; a means for delaying the first timing signal by at least a first delay to produce a second timing signal, the means for delaying the first timing signal including a logic gate that receives the second timing signal and is serially connected to one or more buffer circuits to generate a delayed first timing signal; a means for capturing the data from the data signal in response to the delayed first timing signal; a means for delaying the data signal to generate a delayed data signal; and a means for controlling the first delay based on a phase comparison between the delayed data signal and the delayed first timing signal.

17 . The memory controller of claim 16 , wherein the means for delaying the first timing signal;
delays the first timing signal by the first delay to generate the second timing signal, wherein the first delay is controlled based on the phase comparison.

18 . The memory controller of claim 17 , wherein the means for delaying the first timing signal further comprises:
a means for receiving the second timing signal and outputting a third timing signal in response to a control signal, wherein the third timing signal and the control signal are

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Leibowitz Brian
• Zerbe Jared

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title