Data transmission using delayed timing signals

Patent metadata

Field	Value
Publication number	US-10700671-B2
Application number	US-201715824892-A
Country	US
Kind code	B2
Filing date	Nov 28, 2017
Priority date	Nov 1, 2011
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first interface circuit to receive data accessed from a memory circuit external to the integrated circuit;
a second interface circuit to receive a first timing signal from the memory circuit;
a first circuit to delay the first timing signal by at least a first delay to generate a delayed timing signal, the first circuit including:
a delay circuit to delay the first timing signal by the first delay to generate a second timing signal; and
a buffer circuit to generate the delayed timing signal based on the second timing signal, the buffer circuit providing a second delay between the second timing signal and the delayed timing signal;

a data circuit having an input, the data circuit to capture the data from a data signal at the input in response to the delayed timing signal;
a second circuit to delay the data signal to generate a delayed data signal; and
a control circuit to control the first delay based on a phase comparison between the delayed data signal and the delayed timing signal.

2. The integrated circuit of claim 1 , further comprising:
a phase comparator circuit to compare the delayed timing signal with the delayed data signal to generate a phase comparison signal, the control circuit to control the first delay based on the phase comparison signal.

3. The integrated circuit of claim 1 , the integrated circuit supporting a calibration mode and a normal mode, the control circuit to receive a control signal that enables the control circuit during the calibration mode.

4. The integrated circuit of claim 1 , wherein the first delay is selected so that the delayed timing signal has a quadrature-phase relationship with the data signal.

5. The integrated circuit of claim 1 , wherein the second delay is a non-adjustable delay.

6. The integrated circuit of claim 1 , the first interface circuit to generate a signal that comprises the data, the integrated circuit further comprising:
a circuit to delay the signal generated by the first interface circuit to generate a delayed signal; and
a first multiplexer circuit to receive the delayed signal and the signal generated by the first interface circuit, wherein the first multiplexer circuit generates the data signal by selecting between the delayed signal and the signal generated by the first interface circuit.

7. The integrated circuit of claim 6 , the first circuit comprising:
a second multiplexer circuit to receive the second timing signal and to generate a selected signal based on the second timing signal, the buffer circuit to generate the delayed timing signal based on the selected signal.

8. The integrated circuit of claim 1 , the first interface circuit to generate a signal that comprises the data, the integrated circuit further comprising:
a buffer circuit to delay the signal generated by the first interface circuit to generate the data signal.

9. The integrated circuit of claim 1 , the first interface circuit to receive a signal that comprises the data, wherein the received signal has a delay of at least one bit period of the data relative to the first timing signal.

10. The integrated circuit of claim 1 , wherein the integrated circuit is a processor integrated circuit.

11. A method of operation in an integrated circuit, the method comprising:
receiving data accessed from a memory circuit external to the integrated circuit;
receiving a first timing signal from the memory circuit;
delaying the first timing signal by at least a first delay to generate a second timing signal;
generating a delayed timing signal based on the second timing signal by providing a second delay between the second timing signal and the delayed timing signal;
capturing, with a data circuit having an input, the data from a data signal at the input in response to the delayed timing signal;
delaying the data signal to generate a delayed data signal; and
controlling the first delay based on a phase comparison between the delayed data signal and the delayed timing signal.

12. The method of claim 11 , further comprising:
comparing the delayed timing signal with the delayed data signal to generate a phase comparison signal,
wherein the first delay is controlled based on the phase comparison signal.

13. The method of claim 11 , the integrated circuit supporting a calibration mode and a normal mode, wherein the first delay is controlled during the calibration mode.

14. The method of claim 11 , wherein the first delay is selected so that the delayed timing signal has a quadrature-phase relationship with the data signal.

15. The method of claim 11 , wherein the second delay is a non-adjustable delay.

16. The method of claim 11 , further comprising:
generating a signal that comprises the data; and
delaying the signal that comprises the data to generate the data signal.

17. The method of claim 11 , further comprising:
receiving a signal that comprises the data, wherein the received signal has a delay of at least one bit period of the data relative to the first timing signal.

18. An integrated circuit comprising:
means for receiving data accessed from a memory circuit external to the integrated circuit;
means for receiving a first timing signal from the memory circuit;
a first delay circuit to delay the first timing signal by at least a first delay to generate a second timing signal;
a buffer circuit to generate a delayed timing signal based on the second timing signal by providing a second delay between the second timing signal and the delayed timing signal;
data capturing means having an input, the data capturing means for capturing the data from a data signal at the input in response to the delayed timing signal;
a second delay circuit to delay the data signal to generate a delayed data signal; and
means for controlling the first delay based on a phase comparison between the delayed data signal and the delayed timing signal.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Leibowitz Brian S
• Zerbe Jared

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title