Neural network circuit and neural network system

Patent metadata

Field	Value
Publication number	US-12547883-B2
Application number	US-202217882360-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Feb 7, 2020
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

First claim

What is claimed is:

1 . A neural network circuit, comprising:
a drive circuit configured to convert digital input data into a voltage signal; an input circuit configured to:
send the digital input data to the drive circuit, and
send, to a parameter adjustment circuit, precision information usable to control a first computation precision of an output of a neural network computation preformed on the input data;
a first neural network computation array, comprising a first group of computation units that is configured to perform the neural network computation, based on the voltage signal that represents the input data and pre-stored weights, to obtain a first output current; a first sample-and-hold circuit configured to generate a first analog voltage based on the first output current; the parameter adjustment circuit that is configured to generate a first control signal and a second control signal based on the precision information:
wherein the first control signal is configured to control a slope of a ramp voltage that controls a slope of a ramp voltage and thereby control duration of a first level signal, wherein the first control signal is configured to:
increase the first computation precision by decreasing the slope of the ramp voltage and thereby increase the duration of the first level signal,
decrease the first computation precision by increasing the slope of the ramp voltage and thereby decrease the duration of the first level signal; and

wherein the second control signal is configured to control a frequency at which a first output circuit samples the first level signal, wherein the second control signal is configured to:
increase the first computation precision by increasing the sampling frequency, and
decrease the first computation precision by decreasing the sampling frequency;

a ramp voltage generation circuit, configured to generate the ramp voltage based on the first control signal; a first comparator circuit configured to output the first level signal based on a comparison between the first analog voltage and the ramp voltage; and the first output circuit, configured to:
sample the first level signal based on the second control signal, and
output a first computation result as the output of the neural network computation,
wherein the first computation result is a computation result having the first computation precision, and
wherein the first computation precision is indicated by an information amount sampled by the first output circuit by sampling the first level signal.

2 . The neural network circuit according to claim 1 , wherein:
when the first analog voltage is higher than the reference voltage, the first level signal is a high-level signal; and when the first analog voltage is lower than the reference voltage, the first level signal is a low-level signal.

3 . The neural network circuit according to claim 1 , further comprising a second neural network computation array, wherein the first output circuit is connected to an input end of the second neural network computation array,
wherein the second neural network computation array is configured to compute, based on weights and based on data input into the second neural network computation array, output data; wherein the data input into the second neural network computation array comprises the first computation result, and wherein the first computation result is a pulse signal.

4 . The neural network circuit according to claim 1 , wherein an initial voltage of the ramp voltage is controlled by the first control signal.

5 . The neural network circuit according to claim 1 , wherein the parameter adjustment circuit is further configured to generate a third control signal based on the first computation precision, and
wherein the third control signal is for controlling a reference current of an operational amplifier (OPA) in the first sample-and-hold circuit, to control precision of the first analog voltage and power consumption of the first sample-and-hold circuit.

6 . The neural network circuit according to claim 1 , wherein the parameter adjustment circuit is further configured to control a sampling start time point of the first output circuit.

7 . A neural network system, comprising:
a neural network circuit, comprising:
a drive circuit configured to convert digital input data into a voltage signal;
an input circuit configured to:
send the digital input data to the drive circuit, and
send, to a parameter adjustment circuit, precision information usable to control a first computation precision of an output of a neural network computation preformed on the input data;

a first neural network computation array, comprising a first group of computation units that is configured to perform the neural network computation, based on the voltage signal that represents the input data and pre-stored weights, to obtain a first output current;
a first sample-and-hold circuit configured to generate a first analog voltage based on the first output current;
the parameter adjustment circuit that is configured to generate a first control signal and a second control signal based on the precision information:
wherein the first control signal is configured to control a slope of a ramp voltage that controls a slope of a ramp voltage and thereby control duration of a first level signal, wherein the first control signal is configured to:
increase the first computation precision by decreasing the slope of the ramp voltage and thereby increase the duration of the first level signal,
decrease the first computation precision by increasing the slope of the ramp voltage and thereby decrease the duration of the first level signal; and

wherein the second control signal is configured to control a frequency at which a first output circuit samples the first level signal, wherein the second control signal is configured to:
increase the first computation precision by increasing the sampling frequency, and
decrease the first computation precision by decreasing the sampling frequency;

a ramp voltage generation circuit, configured to generate the ramp voltage based on the first control signal;
a first comparator circuit configured to output the first level signal based on a comparison between the first analog voltage and the ramp voltage; and
the first output circuit, configured to:
sample the first level signal based on the second control signal, and
output a first computation result as the output of the neural network computation,

wherein the first computation result is a computation result having the first computation precision, and
wherein the first computation precision is indicated by an information amount sampled by the first output circuit by sampling the first level signal;
wherein the neural network system further comprises:
a memory, configured to store input data; and
a processor, configured to:
read the input data from the memory, and
input the input data into the neural network circuit, so that the neural network circuit performs neural network computation on the input data.

8 . The neural network system according to claim 7 , wherein
the memory is further configured to store a computer program; and the processor is further configured to invoke the computer program from the memory, to program a neural network computation array in the neural network circuit, wherein the programming is for configuring a weight of the neural network.

9 . The neural network system according to claim 8 , wherein an initial voltage of the ramp voltage is controlled by the first control signal.

10 . The neural network system according to claim 8 , wherein the parameter adjustment circuit is fur

Assignees

• Huawei Tech Co Ltd
• Univ Tsinghua

Inventors

• Gao Bin
• Liu Qi
• Ni Leibin
• Wang Kanwen
• Wu Huaqiang

Classifications

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H03M1/123

  Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title